Table of Contents
- On Board:
- USB JTAG and UART interface ( ), compatible with Xilinx tools (also with many other tools)
- SDIO port expander with voltage-level translation
- 4 x User LEDs
- D1 and D2 are connected to the carrier controller, their function depends on the firmware
- D3 and D4 are connected to the 4 x 5 module B2B connector pins, and are directly controlled by the module
- 1 x User push button
- Connected to "intelligent Carrier Controller (iCC)" and can be used as module reset button. Other usage possible, actual function depend on the code loaded into iCC.
- 4A high efficiency power SoC DC-DC step-down converter with integrated inductor ( ) for 3.3V power supply
- 4 User DIP switches
- Enable/disable update of the "intelligent Carrier Controller"
- MIO0 (readable signal by iCC and module)
- 2 "mode" bits
- Trenz 4 x 5 module socket (3 x )
- Micro SD card connector - Zynq SDIO0 bootable SD port
- 2 x VG96 backplane connectors (mounting holes and solder pads)
- Mini USB connector (USB JTAG and UART interface)
- RJ45 GbE connector
- USB host connector
- Barrel jack for 5V power supply input
- 100 mm x 64.5 mm
- Samtec Razor Beam™ LSHM-150 B2B connector, JB1
- Samtec Razor Beam™ LSHM-150 B2B connector, JB2
- Samtec Razor Beam™ LSHM-130 B2B connector, JB3
- Micro SD card socket with detect switch, J3
- LED indicators D1 and D2
- Mini-USB type B connector, J4
- LED indicators D3 and D4
- Configuration DIP switches, S2 (see table under "DIP switches" section)
- User push button (Reset), S1
- External connector (VG96) placeholder, J1
- External connector (VG96) placeholder, J2
- VCCIO voltage selection jumper block, J5, J8, J9 and J10 (see "Power and Power-On Sequence" section)
- Trxcom 1000Base-T Gigabit RJ45 Magjack, J14 with 4 integrated LEDs
- USB type A receptacle, J6 (optional micro USB 2.0 type B receptacle available, J12)
- 5V power connector jack, J13
- SD IO voltage (VCCA) selection jumper J11
Initial Delivery State
Storage device name
|FTDI chip configuration EEPROM U10||Xilinx License|
Do not overwrite, see warning in related section
|System Controller CPLD U5||SC CPLD Firmware||-|
Board is shipped in following configuration:
- VCCIO voltage selection jumpers are all set to 1.8 V.
- SD IO Voltage jumper J11 is set to 1.8V.
- S1 switch configured as reset button in CPLD.
- Two VG96 backplane connectors are not soldered to the board, but they are included in the package as separate components.
- S2 DIP switches are configured as follows:
|S2-1||ON||Mode control MC1.|
|S2-2||ON||FPGA access on module (need also S2-3 ON)|
|ON||FPGA access on module (need also S2-2 ON)|
|S2-4||OFF||Boot mode set to QSPI.|
Different delivery configurations are available upon request.
The configuration signals are managed by the CPLD and therefore Firmware dependet. Standart configuration is given below.
Switch /Button/ LED /Pin
|Signal Schematic Names||Connecte to||Functionality||Notes|
|Module JTAG select||Dip switche S2-2||CM0||SC CPLD pin 75|
ON: Module JTAG access ( if S2-3 ON)
OFF: Module CPLD JTAG access ( if S2-3 ON)
|TE0703 CPLD - CC703S#CC703S-JTAG|
|Module JTAG select||SC CPLD pin 104||PROGMODE||B2B JB1 pin 90||Module JTAG select: Module CPLD high or SoC/FPGA JTAG low ; via CPLD firmware linked to CM0||TE0703 CPLD - CC703S#CC703S-JTAG|
|Carrier CPLD JTAG enable|
Dip switch S2-3
|SC CPLD pin 120|
ON: SoM JTAG access
OFF: Carrier SC CPLD JTAG access
|TE0703 CPLD - CC703S#CC703S-JTAG|
|Select boot mode||Dip switche S2-4||MIO0|
SC CPLD pin 94
and B2B JB1 pin 88
ON: Boot from SD Card
OFF: Boot from QSPI flash on module
|TE0703 CPLD - CC703S#CC703S-BootMode|
Boot Mode is also module dependent
|Select boot mode||SC CPLD pin 83|
|B2B JB1 pin 31||SD-CARD (Zynq) or QSPI-Flash; via CPLD firmware linked to MIO0||TE0703 CPLD - CC703S#CC703S-BootMode|
Boot Mode is also module dependent
|Reset||S1||S1||SC CPLD pin114||global reset||TE0703 CPLD - CC703S#CC703S-Reset|
|Reset||SC CPLD pin 119||RESIN||B2B JB2 pin 17||via CPLD firmware linked to S1||TE0703 CPLD - CC703S#CC703S-Reset|
|Moduel enable||SC CPLD pin 81|
|B2B JB1 pin 27||Module power enable||pulled up by CPLD|
|Disable CPLD power Management||SC CPLD pin 78||NOSEQ||B2B JB1 pin 8||Disable CPLD power management||pulled up by CPLD|
|Disable Card detect pin||Dip switche S2-1|
|SC CPLD pin 76|
ON: Force CD Pin to module to GND
OFF: Set CD Pin to module to SD CD Pin
|TE0703 CPLD - CC703S#CC703S-SD|
|SD Card detect||SD Card Socket J3 pin 9||SD_CD||SC CPLD pin93||Low if Card detected||TE0703 CPLD - CC703S#CC703S-SD|
|SD Selector||SC CPLD pin 113||SD_SEL||U2 pin 24||FIXed to GND: Select SD Card (CPLD SD port not used)||TE0703 CPLD - CC703S not used|
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the B2B connector:
|B2B Connector||Interfaces||I/O Signal Count||Notes|
|JB1||User IO||48 single ended or 24 differential||Available on J1|
|I²C||2||MIO10, MIO11, available on J1|
|primary UART||2||MIO14, MIO15; CPLD Firmware dependent|
|secondary UART||2||MIO12, MIO13; CPLD Firmware dependent|
|Control Signals||7||including MIO0 and MIO9; CPLD Firmware dependent|
|JB2||User IO||36 single ended or 18 differential||Available on J1|
|USB OTG||5||Including USB-VBUS and VBUS_V_EN|
|JB3||User IO||66 single ended or 33 differential||Available on J2|
Micro SD Card Socket
Micro SD card socket is connected to the B2B connector through a Texas Instruments TXS02612 SDIO port expander for voltage translation. The Micro SD card has 3.3V signal voltage level while most 4 x 5 modules use 1.8V for the SD card interface.
|Connected To||Signal Name||Notes|
|U5-93||SD-CD||Managed CPLD Firmware|
TE0703 board has two physical USB sockets:
- J4 as mini-USB type B socket wired to the on-board FTDI FT2232H chip.
- J6 as USB type A wired to B2B connector JB3 (USB transceiver used depends on the SoM model used). Instead of J6, a micro USB connector J12 can be assembled
|USB Connector||Signal||Connected to|
|J6 or J12||OTG-D_P||JB3-48|
On-board Ethernet jack J14 pins are routed to B2B connector JB1. Ethernet jack J14 LED signals PHY_LED1, PHY_LED2, PHYLED1R and PHYLED2R are all routed to System Controller CPLD bank 1.
Ethernet PHY connection
External VG96 Connector I/Os
I/O signals connected to the B2B connector:
|B2B Connector||Interfaces||I/O Signal Count||Notes|
|J1||User IO||48 single ended or 24 differential||From JB1 (group1)|
|User IO||36 single ended or 18 differential||From JB3 (group2)|
|J2||User IO||48 single ended or 24 differential||From JB2 (group4)|
|User IO||18 single ended or 9 differential||From JB2 (group3)|
|CPLD User IO||18 single ended||Including UART 2 on X16, X17; CPLD Firmware dependent|
USB to JTAG and UART bridge
TE0703 has on-board USB JTAG and UART solution based on UART/FIFO controller from FTDI (U4). FTDI EEPROM is pre-programmed with license code to support Xilinx programming tools.
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
JTAG and UART signals along with some more FTDI IOs are routed to the CPLD. See CPLD Firmware TE0703 CPLD - CC703S#CC703S for further description.
B2B Connector Pin
|M_TCK||U5-131||CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, dependent on Dip switches linked to Module JTAG Port on JB2.|
|FT_B_TX||U5-139||CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, linked to Module primary UART on JB1.|
|ADBUS7||U5-142||CPLD Firmware dependent TE0703 CPLD - CC703S#CC703S, currently not used.|
TE0703-06 has a Lattice LCMXO2-1200HC as a system controller. for further function description see Firmware TE0703 CPLD - CC703S#CC703S,
SD IO Levelshifter
SD IO levelshifter (U2) is used in congntion with jumper J11 to select the correct SD IO interface voltage of the SoM.
For power squenz reasons the I2C bus is routed via a repater (U7) to to ensure no IOs of the SoM are driven before M3.3VOUT is up.
There are four on-board LEDs. D3 and D4 are connected to the B2B connector JB2 pins FLED1 and FLED2 respectively and can be read by CPLD firmware. See TE0703 CPLD - CC703S#CC703S-LED.
|D1||Red||ULED1||U5-117||FTDI UART receive activity.|
|D2||Green||ULED2||U5-115||FTDI UART transmit activity.|
|D3||Red||FLED1||JB2-99||Module LED, CPLD can read status via signal FL_0 connected via 10K.|
|D4||Green||FLED2||JB2-90||Module LED, CPLD can read status via signal FL_1 connected via 10K.|
DIP switch settings are CPLD Firmware dependent, default firmware:
|S2-1||Set PGOOD pin to low ('0') / Force CD pin to module to high impedance ('Z')||Set PGOOD pin to high ('1') / Set CD pin to module to SD_CD pin||TE0703 CPLD - CC703S#CC703S-BootMode / TE0703 CPLD - CC703S#CC703S-SD|
|S2-2||Module FPGA JTAG access ( if S2-3 ON)||Module CPLD JTAG access ( if S2-3 ON)||TE0703 CPLD - CC703S#CC703S-JTAG|
|S2-3||Module FPGA/CPLD JTAG access (depends on S2-2)||Carrier CPLD JTAG access||TE0703 CPLD - CC703S#CC703S-JTAG|
|S2-4||Boot from SD Card (Set pin to GND)||Boot from QSPI flash on module (Set pin to VDD)|
TE0703 CPLD - CC703S#CC703S-BootMode
Mode status is displayed on TE0703 LEDs, see TE0703 CPLD - CC703S#CC703S-LED.
TE0703-06 has 5 Voltage selection jumpers. Select 1.8V or 3.3V in accordenc of the attached module capabilities and your needs. Refer to the 4 x 5 Module Integration Guide for VCCIO voltages options.
|VCCA||J11||1-2||2-3||SD IO level shifter voltage selection (module side), compare with TRM of attached Module|
Take care of the VCCO voltage ranges of the particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.
It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.
Power supply with minimum current capability of 3A for system startup is recommended.
Single power supply with minimum current capability of 3A at 5V for system startup is recommended.
|Power Input Pin||Max Current|
|VIN (power connector jack J13)||4A|
Typical power consumption for TE0703-05 + TE0715-01 module with SD micro card inserted, Ethernet connected and link up, system booted into Linux prompt and idling is 5V / 0.55A.
It is not allowed to feed any voltage to any external I/O pin before there is no power indication on M3.3VOUT pins. Presence of 3.3V on B2B JB2 connector pins 9 and 11 indicates that module is properly powered up and ready.
If any of the VCCIOA, VCCIOB, VCCIOC or VCCIOD will be powered through external connectors J1 or J2, then corresponding VCCIO jumper should also be removed.
|Power Rail Name|
|5VIN||J13-1||in||5 V power input|
|VIN||-||-||5 V power input after protection|
|3.3V||JB1-2, 4, 6, 14, 16||out||Generatet from VIN by DCDC U3, constant 3.3V rail|
|M1.8VOUT||JB1-40||in||1.8V from Module.|
|M3.3VOUT||JB2-9, 11||in||3.3V from Module.|
|VCCIOA||JB1-10, 12||out||Use jumper J5 to source by M1.8VOUT or M3.3VOUT.|
|VCCIOB||JB2-2 ,4||out||Use jumper J8 to source by M1.8VOUT or M3.3VOUT.|
|VCCIOC||JB2-6||out||Use jumper J9 to source by M1.8VOUT or M3.3VOUT.|
|JB2-8, 10||out||Use jumper J10 to source by M1.8VOUT or M3.3VOUT.|
|VCCA||-||-||SD IO leveshifter voltge on Module side. Use jumper J11 to source by M1.8VOUT or M3.3VOUT.|
|VCCJTAG||JB2-92||in||JTAG reference voltage|
|USB-VBUS_R||J6-1 (J12-1)||out||5V USB, derived from VIN by power switch U1|
Board to Board Connectors
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
- 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
- 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
|Order number||Connector on baseboard||compatible to||Mating height|
The module can be manufactured using other connectors upon request.
Connector Speed Ratings
The LSHM connector speed rating depends on the stacking height; please see the following table:
|Stacking height||Speed rating|
|12 mm, Single-Ended||7.5 GHz / 15 Gbps|
|12 mm, Differential|
6.5 GHz / 13 Gbps
|5 mm, Single-Ended||11.5 GHz / 23 Gbps|
|5 mm, Differential||7.0 GHz / 14 Gbps|
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
Absolute Maximum Ratings
5VIN supply voltage
|MP5010A, EN6347QI data sheet|
|ROHM Semiconductor SML-P11 Series datasheet|
Recommended Operating Conditions
5VIN supply voltage
|USB2.0 specification concerning 'VBUS' voltage|
|FTDI FT2232H datasheet|
Board size: 100 mm × 64.5 mm. Notice that the mini-USB jack on the left and ethernet RJ-45 jack on the right are hanging slightly over the edge of the PCB making the total width of the longer side approximately 106 mm. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8 mm
PCB thickness: 1.65 mm
Highest parts on the PCB are USB type A jack and ethernet RJ-45 jack, approximately 15 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Operating Temperature Ranges
The carrier board itself is capable to be operated at industrial grade temperature range.
Please check the operating temperature range of the mounted modules which determines the relevant operating temperature range of the overall system.
42g - Plain board.
13g - 2 x VG96 connectors.
Currently Offered Variants
Hardware Revision History
Added SD IO voltage selection jumper
Further changes see PCN.
Added VCCIO Jumpers
Corrected FTDI EEPROM connection
Added VCCIO strapping resistors
First series boards
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Document Change History
Jan Kumann, John Hartfiel
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