Page History
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Name / opt. VHD Name | Direction | Pin | Description | ||||
---|---|---|---|---|---|---|---|
DONE | in | 13 | FPGA DONE signal | ||||
EN_SC3 | in | 16 | |||||
F_TCK / C_TCK | out | 28 | JTAG FPGA | ||||
F_TDI / C_TDI | out | 27 | JTAG FPGA | ||||
F_TDO / C_TDO | in | 23 | JTAG FPGA | ||||
F_TMS / C_TMS | out | 25 | JTAG FPGA | ||||
JTAGSEL | in | 26 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | ||||
MODE_SC1 | in | 11 | |||||
NOSEQ_SC4 | 12 | ||||||
nRST_SC0 | in | 8 | |||||
PG_ALL | in | 10 | |||||
PROG_B | out | 17 | FPGA PROG_B Reset | ||||
PWR_DIS | out | 5 | |||||
STAT_SC2 | out | 14 | |||||
SYSLED1 / LED1 | out | 9 | |||||
TCK_SC7 / M_TCK | in | 30 | JTAG B2B | ||||
TDI_SC6 / M_TDI | in | 32 | JTAG B2B | ||||
TDO_SC5 / M_TDO | out | 1 | JTAG B2B | ||||
TMS_SC8 / M_TMS | in | 29 | JTAG B2B | ||||
UFL | out | 4 | |||||
UI_CLK / XB_SC | out | 20 | |||||
UIO / XA_SC | in | 21 |
Functional Description
JTAG
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Overview
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