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Firmware for PCB CPLD with designator U4. CPLD Device in Chain: LCMX02-256HC
Feature Summary
- JTAG
- Reset
- Power
- LED
- USER IO
- Power Management
- ...
Firmware Revision and supported PCB Revision
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Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
Reset
PROG_B is nRST_SC0 and PG_ALL and EN_SC3 after power on delay.
Power
Power Good (STAT_SC2) is PGALL and EN_SC3.
USER IO
MODE_SC1 is connected to XB_SC.
XA_SC is connected to UFL.
LED
Green LED D2
| Status | Description |
|---|---|
| On | Done is low, FPGA not programmed |
| OFF | Done is high, FPGA is programmed |
Red LED D1
| Status | Condition | Description |
|---|---|---|
| Blinking | POR_B is low | nRST_SC0 or PG_ALL or EN_SC3 is low |
| User Defined | POR_B is high | XA_SC is connected to LED |
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV02 |
| Work in progressREV01 , Firmware released 2015-04-17 | ||||||||||||||||||||||
| 2018-03-21 | v.1 | REV01 | REV02 |
| Initial release | ||||||||||||||||||||||
| All |
|
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Overview
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