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Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional Microblaze MicroBlaze is add for Hello TE0741 example.

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DateVivadoProject BuiltAuthorsDescription
2018-04-162017.4TE0741-test_board-vivado_2017.4-build_07_20180416142156.zip
TE0741-test_board_noprebuilt-vivado_2017.4-build_07_20180416142217.zip		John Hartfiel
  • initial release

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Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Connect JTAG and power on PCB
  2. Open Vivado HW Manager
  3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB
  3. Prepare HW like described on section Programming
  4. Connect UART USB (most cases same as JTAG)
  5. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, Hello TE0741 from Bitfile Firmware Example will be run on UART console.
              Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART

Open Serial Console (e.g. putty)

  1. Speed: 9600
  2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

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Vivado HW Manager: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (MGT...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. MGT REFREFCL1~125MHz, MIGGT_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
    3. Additional Infos: System reset from MCS and GIO outputs
    4. REFCLK3~156,25MHz (default off, configured with MCS Firmware)
    5. LED_D1/D2 control
    6. SI5338 25MHz REF CLK Enable
    7. MGT Power Monitoring+MGT Enable

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System Design - Vivado

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Block Design

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Constrains

Basic module constrains

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Code Block
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title_i_io.xdc
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#LED
set_property PACKAGE_PIN D26 [get_ports {LED_D1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D1[0]}]
set_property PACKAGE_PIN E26 [get_ports {LED_D2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D2[0]}]
#MGT Power
set_property PACKAGE_PIN G25 [get_ports {PG_MGT_1V2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V2[0]}]
set_property PACKAGE_PIN K23 [get_ports {PG_MGT_1V[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V[0]}]
set_property PACKAGE_PIN H22 [get_ports {EN_MGT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {EN_MGT[0]}]
#SI5338 CLK
set_property PACKAGE_PIN C26 [get_ports {CLK_EN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK_EN[0]}]
#I2C PLL SI5338
set_property PACKAGE_PIN A20 [get_ports ext_scl_o]
set_property IOSTANDARD LVCMOS33 [get_ports ext_scl_o]
set_property PACKAGE_PIN B21 [get_ports ext_sda]
set_property IOSTANDARD LVCMOS33 [get_ports ext_sda]
Code Block
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title_i_timing.xdc
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#Fmeter can be ignored, it's only simple measurement

set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]

set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTC}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTA}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTB}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEALUMODE}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTCTRL}]


set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}]

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