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Refer to for the current online version of this manual and other available documentation.

This example shows how to reconfigure SI5338 with the MicroBlaze_MCS and monitor the CLKs. An additional MicroBlaze is added for the Hello_TE0741 standalone application.

Key Features

  • Vitis/Vivado 2021.2
  • MicroBlaze
  • I2C
  • UART
  • Flash
  • FMeter
  • SI5338 initialisation with MCS

Revision History

DateVivadoProject BuiltAuthorsDescription


  • pll_in4 i2c address pin pulled to GND in System controller ip
  • added new variants
  • update 2021.2
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------
Known Issues



Vitis2021.2needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0741-03-070-2IF  070_2if REV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-160-2IF160_2ifREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-325-2IF325_2ifREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-410-2IF410_2ifREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-070-2CF070_2cfREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-160-2CF160_2cfREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-325-2CF*325_2cfREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-410-2CF410_2cfREV02, REV03---32MBMGT LR: 6,6 Gb/s
TE0741-03-160-2C1160_2c1REV02, REV03---32MBMGT LR: 10,3125 Gb/s
TE0741-02-B3E-1-AF160_3e1REV02, REV03---32MBMGT LR: 10,3125 Gb/s
TE0741-04-A2I-1-A070_2ifREV04---32MBMGT LR: 6,6 Gb/s
TE0741-04-G2C-1-A410_2cfREV04---32MBMGT LR: 6,6 Gb/s
TE0741-03-S002410_2cfREV03---32MBMGT LR: 6,6 Gb/s

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

*used as reference

Additional Hardware


For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
Design sources

Additional Sources

SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
Additional design sources





BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Xilinx Support Archive *.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File



Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)



File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebuilt content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Generate Programming Files with Vitis
    1. Run on Vivado TCL:

      Script generates applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      TE::sw_run_vitis -all
    2. Copy "\prebuilt\software\<short name>\hello_te0741.elf" into  "\firmware\microblaze_0\"
    3. (optional) Copy "\prebuilt\software\<short name>\scu.elf" into  "\firmware\microblaze_mcs_0\"
    4. Regenerate Vivado Project or Update Bitfile only, with new "hello_te0741.elf" and "scu.elf"

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0741

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

SD-Boot mode

Not used on this Example.


  1. Connect JTAG and power on PCB
  2. Open Vivado HW Manager
  3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI as Boot Mode

    Note: See TRM of the Carrier, which is used.

  4. Power On PCB

    1. FPGA Loads Bitfile from Flash

    2. MCS Firmware configure SI5338 and starts Microblaze

    3. Hello TE0741 from Bitfile Example will be run on UART console.

      info: Do not reboot, if Bitfile programming over JTAG is used as programming method.


    Open Serial Console (e.g. putty)

    1. Speed: 9600
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
    • LED_D1/D2 control
    • SI5338 25MHz REF CLK Enable
    • MGT Enable
  • Monitoring:
    • Set radix from VIO signals (MGT...) to unsigned integer.
    • Note: Frequency Counter is inaccurate and displayed unit is Hz
    • MGT REFCLK1~125MHz, GT_REFCLK3~156,25MHz (default off, configured with MCS Firmware)
    • MGT Power Monitoring
Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design


Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constraints

set_property PACKAGE_PIN D26 [get_ports {LED_D1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D1[0]}]
set_property PACKAGE_PIN E26 [get_ports {LED_D2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D2[0]}]
#MGT Power
set_property PACKAGE_PIN G25 [get_ports {PG_MGT_1V2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V2[0]}]
set_property PACKAGE_PIN K23 [get_ports {PG_MGT_1V[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V[0]}]
set_property PACKAGE_PIN H22 [get_ports {EN_MGT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {EN_MGT[0]}]
#SI5338 CLK
set_property PACKAGE_PIN C26 [get_ports {CLK_EN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK_EN[0]}] #I2C PLL SI5338
#I2C PLL SI5338
set_property PACKAGE_PIN A20 [get_ports ext_scl_o]
set_property IOSTANDARD LVCMOS33 [get_ports ext_scl_o]
set_property PACKAGE_PIN B21 [get_ports ext_sda]
set_property IOSTANDARD LVCMOS33 [get_ports ext_sda]
set_property PACKAGE_PIN B20 [get_ports pll_in4_i2c_address]
set_property IOSTANDARD LVCMOS33 [get_ports pll_in4_i2c_address]

set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN L23 [get_ports reset]
set_property PACKAGE_PIN C23 [get_ports qspi_flash_ss_io]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_ss_io]
set_property PACKAGE_PIN B24 [get_ports qspi_flash_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_io0_io]
set_property PACKAGE_PIN A25 [get_ports qspi_flash_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_io1_io]
set_property PACKAGE_PIN B22 [get_ports qspi_flash_io2_io]
set_property PACKAGE_PIN A22 [get_ports qspi_flash_io3_io]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_io2_io]
set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_io3_io]
#Fmeter can be ignored, it's only simple measurement

set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]

set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTC}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTA}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTB}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEALUMODE}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTCTRL}]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks mgt_clk1_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks mgt_clk3_clk_p]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


MCS Firmware to configure SI5338 and Reset System.

Template location: \sw_lib\sw_apps\scu

Hello TE0741

Xilinx Hello World example as endless loop

Template location: \sw_lib\sw_apps\hello_te0741

Additional Software


File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

App. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

DateDocument Revision



  • pll_in4 - i2c address pin pulled to zero in System Controller ip
  • added new variants


Waldemar Hanemann

  • update 2021.2
2018-05-15v.7John Hartfiel

  • Release 2017.4
  • small description update


John Hartfiel

  • initial release
Document change history.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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