Page History
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Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
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0 | 505 | GTR |
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1 | 505 | GTR |
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2 | 505 | GTR |
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3 | 505 | GTR |
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Table 4: MGT lanes.
There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
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Power Rail Name on B2B Connector | JM1 Pins | JM2 Pins | Direction | Notes |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board. |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board. |
1.8V | 39 | - | Output | Internal 1.8V voltage level. |
JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" |
VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage. |
VCCO_65 | - | 5 | Input | High performance I/O bank voltage. |
VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage. |
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Module Variant | MPSoC | RAM | SPI Flash | Temperature Range | Note | |
---|---|---|---|---|---|---|
TE0820-02-02CG-1E | XCZU2CG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | ||
TE0820-02-03CG-1E | XCZU3CG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | ||
TE0820-02-02EG-1E | XCZU2EG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | ||
TE0820-02-03EG-1E | XCZU3EG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | ||
TE0820-02-02EG-1E3 | XCZU2EG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | 2,5mm Samtec connector | |
TE0820-02-03EG-1E3 | XCZU3EG-1SFVC784E | 1 GByte DDR4 | 64 MByte | Extended | 2,5mm Samtec connector |
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Table 19: Recommended operating conditions.
Note |
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See Xilinx datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips. |
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Date | Revision | Notes | PCN Link | Documentation Link | |
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2017-08-17 | 02 | -- | TE0820-02 | ||
2016-12-23 | 01 | Prototype only | TE0820-01 |
Table 20: Hardware revision history table.
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Date | Revision | Contributors | Description | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
| John Hartfiel |
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2017-11-20 | v.51 | John Hartfiel |
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2017-11-10 | v.50 | John Hartfiel |
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2017-10-18 | v.49 | John Hartfiel |
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2017-09-25 | v.48 | John Hartfiel |
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2017-09-18 | v.47 | John Hartfiel |
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2017-08-30 | v.46 | Jan Kumann |
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2017-08-24 | v.36 | John Hartfiel |
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2017-08-21 | v.34 | John Hartfiel |
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2017-08-21 | v.33 | Jan Kumann |
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2017-08-18 | v.7 | John Hartfiel |
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2017-08-07 | v.5 | Jan Kumann | Initial version. |
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