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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Design supports following carriers:

Additional HW Requirements:

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File               

Additional Sources

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Prebuilt

<!-- 

<table width="100%">
<tr> <th>File                                </td> </th>tr>
<tr> <th>File<td>BIN-Extension</th>File  <th>Description                           </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </th>td> </tr>
<tr> <td>BIF<td>BIT-File                             </td> <td>*.bifbit         </td>  <td>File with description to generate Bin-File  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>BIN<td>DebugProbes-File                     </td> <td>*.ltx         </td> <td>*.bin  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image  <td>Flash  Configuration File with Boot-Image (Zynq-FPGAs)              </td> <td>*.img         </td>  <td>Debian Image for SD-Card       </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File            </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats           </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface    </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI    </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card</tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                    </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---</tr>
<tr> <td>MCS-File         </td>  <td>Report files in different formats              </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA    part only)                  </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf<td>MMI-File          </td>  <td>Exported Vivado Hardware Specification for SDK/HSI            </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS          </td> </tr>
<tr> <td>LabTools Projector BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image        </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File      </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf    </td> </tr>
<tr> <td>MCS-File                </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                  </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)</tr>
<tr> <td>SREC-File                            </td> </tr>
<tr> <td>MMI-File<td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                </td> <td>*.mmi         </td> </tr> <td>File  with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

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File

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File-Extension

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Description

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

 
</table>
-->

*.srec

Converted Software Application for MicroBlaze Processor Systems 

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

• TE0841 "Test Board" Reference Design

Design Flow

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Basic Design Steps
Add/ Remove project specific 
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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate MCS Firmware (optional):
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
   3. Select Release Built
   4. Regenerate App
7. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
8. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
9. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
10. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"
11. Generate MCS file with Bitfile and application for SREC Bootloader
    
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_hsi
       Note: SREC convertion from *.elf to *.srec will be done by scripts, alternative use SDK, see SDK Projects

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on PCB
2. (if not done)

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

• TE0741 "Test Board" Reference Design

Design Flow

<!--
Basic Design Steps
Add/ Remove project specific 
  -->

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
   Note: Select correct one, see TE Board Part Filesor open with "vivado_open_project_guimode.cmd", if generated.
5. Type on Vivado ConsoleCreate HDF and export to prebuilt folder
   Run on Vivado TCL: TE::hwpr_program_buildflash_design mcsfile -exportswapp hello_prebuiltte0841
   Note: Script generate design and export files into \Alternative use SDK or setup Flash on Vivado manually
6. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

1. Connect JTAG and power on PCB
2. Open Vivado HW Manager
3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
4. Generate MCS Firmware (optional):
   1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
   2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
   3. Select Release Built
   4. Regenerate App
5. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
6. Copy "\prebuilt\software\<short name>\hello_te0741.elf" into  "\firmware\microblaze_0\"
7. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
8. Regenerate Vivado Project or Update Bitfile only with "hello_te0741.elf" and "scu.elf"

Launch

Programming

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Description of Block Design, Constrains...
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on PCB
2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
   Note: Alternative use SDK or setup Flash on Vivado manually
4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

1. Connect JTAG and power on PCB
2. Open Vivado HW Manager
3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Power on PCB
   Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, Hello TE0741 from Bitfile Example will be run on UART console.
             Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART

Open Serial Console (e.g. putty)

1. Speed: 9600
2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

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Vivado HW Manager: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals (MGT...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
   2. MGT REFCL1~125MHz, GT_REFCLK3~156,25MHz (default off, configured with MCS Firmware)
   3. LED_D1/D2 control
   4. SI5338 25MHz REF CLK Enable
   5. MGT Power Monitoring+MGT Enable
      

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System Design - Vivado

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Block Design

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Constrains

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1. "
   1. Note SREC Bootloader try to find application on flash, this will stop, if Flash is empty.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Power on PCB
   Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts MicroBlaze, MicroBlaze SREC Bootloader loads Hello TE0781 from Flash into RAM and starts application. Example will be run on UART console.
             Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART

Open Serial Console (e.g. putty)

1. Speed: 9600
2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

Image Added

Vivado HW Manager: 

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals (fm_si...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
   2. SI will be configured with MCS firmware, default all off on PCB REV01
   3. LED control via VIO
   4. MGT CLK Freq can be changed over BUFG_GT control signals divider
   5. MCS Reset possible via VIO
      

Image Added

System Design - Vivado

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Block Design

Image Added

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
create_clock -name ddr4_0_clk -period 4.95 [get_pins */ddr4_0/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -name ddr4_1_clk -period 4.95 [get_pins */ddr4_1/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*]] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DTS[*]] 1.000

#LED
set_property PACKAGE_PIN D26 [get_ports {LED_D1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D1[0]}]
set_property PACKAGE_PIN E26 [get_ports {LED_D2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_D2[0]}]
#MGT Power
set_property PACKAGE_PIN G25 [get_ports {PG_MGT_1V2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V2[0]}]
set_property PACKAGE_PIN K23 [get_ports {PG_MGT_1V[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PG_MGT_1V[0]}]
set_property PACKAGE_PIN H22 [get_ports {EN_MGT[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {EN_MGT[0]}]
#SI5338 CLK
set_property PACKAGE_PIN C26 [get_ports {CLK_EN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK_EN[0]}]
#I2C PLL SI5338
set_property PACKAGE_PIN A20 [get_ports ext_scl_o]
set_property IOSTANDARD LVCMOS33 [get_ports ext_scl_o]
set_property PACKAGE_PIN B21 [get_ports ext_sda]
set_property IOSTANDARD LVCMOS33 [get_ports ext_sda]

#Fmeter can be ignored, it's only simple measurement

set_false_path -from [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_05/U0/FMETERBUFG_GT_genO[*].COUNTER_F_inst/bl.DSP48E_2/CLK0]}] -to [get_clocks -of_objects [get_pins {msys_i/labtoolsclk_fmeterwiz_0/U0inst/F_reg[*]/D}]

mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_06/U0/toggle_reg/CBUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins {msys_i/labtoolsclk_fmeterwiz_0/U0inst/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTC}mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/labtoolsclk_fmeterwiz_0/U0inst/togglemmcme3_adv_reginst/CCLKOUT0]] -to [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_06/U0/FMETERBUFG_GT_genO[*].COUNTER_F_inst/bl.DSP48E_2/RSTA0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/labtoolsclk_fmeterwiz_0/U0inst/togglemmcme3_adv_reginst/CCLKOUT0]] -to [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_05/U0/FMETERBUFG_GT_genO[*].COUNTER_F_inst/bl.DSP48E_2/RSTB0]}]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/labtoolsclk_fmeterwiz_0/U0inst/togglemmcme3_adv_reginst/CCLKOUT0]] -to [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_01/U0/FMETERIBUF_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEALUMODEOUT[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/labtoolsclk_fmeterwiz_0/U0inst/togglemmcme3_adv_reginst/CCLKOUT0]] -to [get_pinsclocks {msys_i/labtoolsutil_ds_fmeterbuf_04/U0/FMETERIBUF_genOUT[*].COUNTER_F_inst/bl.DSP48E_2/RSTCTRL}]


set_false_path -from0]}]
set_false_path -from [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_10/inst/mmcmmmcme3_adv_inst/CLKOUT0]]
set_false_path -tofrom [get_clocks {msys_i/util_ds_buf_04/U0/IBUF_OUT[0]}]
set_false_path -fromto [get_clocks -of_objects [get_pins msys_i/clk_wiz_10/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}mmcme3_adv_inst/CLKOUT0]]

Software Design - SDK/HSI

...

Template location: \sw_lib\sw_apps\scu

Hello

...

TE0841

Xilinx Hello World example as andless endless loop

Template location: \sw_lib\sw_apps\hello_te0741te0841

SREC SPI Bootloader

Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code

Template location: \sw_lib\sw_apps\srec_spi_bootloader

                               \sw_lib\sw_services\xilisf_v5_9

Additional Software

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