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Example shows, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze with Linux example.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2021.2
  • PetaLinux
  • MicroBlaze
  • UART
  • Flash
  • FMeter
  • SI5338 initialisation with MCS

Revision History

DateVivadoProject BuiltAuthorsDescription
Waldemar Hanemann
  • new spi bootloader by Henrik Brix Andersen
  • fixed SC0841 bugs
John Hartfiel
  • new Assembly variants
  • add Linux

John Hartfiel
  • REV02 Board parts
  • new SI5338 configuration (default REV02)
  • change xilisf_v5_9 for N25Q512A11G1240E support
  • Some changes on block design
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------
Known Issues



Vitis2021.2needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0841-01-035-1C   01_35_1c_1gb   REV01    1GB      32MB       NA         NA       NA               
TE0841-01-035-1I   01_35_1i_1gb   REV01    1GB      32MB       NA         NA       NA               
TE0841-01-035-2I   01_35_2i_1gb   REV01    1GB      32MB       NA         NA       NA               
TE0841-01-040-1C   01_40_1c_1gb   REV01    1GB      32MB       NA         NA       Serial number 512479 up tp 512474  has same 64MB Flash like REV02
TE0841-01-040-1I   01_40_1i_1gb   REV01    1GB      32MB       NA         NA       NA               
TE0841-02-035-1C   02_35_1c_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-035-1I   02_35_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-035-2I   02_35_2i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-040-1C   02_40_1c_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-040-1I   02_40_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-040-1IL  02_40_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-31C21-A  02_35_1c_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-31I21-A  02_35_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-32I21-A  02_35_2i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-41C21-A  02_40_1c_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-41I21-A  02_40_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 
TE0841-02-41I21-L  02_40_1i_2gb   REV02    2GB      64MB       NA         NA       PLL programmed 

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes
TE0706used as reference carrier

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
heat sinkHeat sink is recommended urgently

*used as reference

Additional Hardware


For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
Additional design sources





BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File



Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)



File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems



Converted Software Application for MicroBlaze Processor Systems

Prebuilt files (only on ZIP with prebuilt content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/ and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

      Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0xB00000 (increase automatically generate Boot partition), see TE0841 Test Board#Config

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files(uboot.elf and image.ub) to prebuilt folder
    • copy u-boot.elf and image.ub "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  8. Generate Programming Files with Vitis(Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis) 

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

  9. (optional) Update spi_bootloader.elf and/or scu_te084.elf

    1. Copy "\prebuilt\software\<short name>\spi_bootloader.elf" into  "\firmware\microblaze_0\"
    2. Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
    3. Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf" and "scu_te0841.elf"



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/ and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)

  1. Connect the USB cable(JTAG) and power supply on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
    Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

  3. Reboot (if not done automatically)

SD-Boot mode

Not used on this Example.


Not used on this example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI as Boot Mode

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. FPGA Loads Bitfile from Flash

    2. MCS Firmware configure SI5338 and starts Microblaze

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR

    4. U-boot loads Linux from QSPI Flash into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 9600
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Boot process takes a while, please wait...

  3. You can use Linux shell now.

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
    • SI will be configured with MCS firmware, default all off on PCB REV01,  PCB REV02 SI5338 will be preconfigured.
    • LED control via VIO
    • MGT CLK Freq can be changed over BUFG_GT control signals divider
    • MCS Reset possible via VIO
    • MIG Reset is possible over VIO
    • MCS can be disabled over VIO (For PCB REV01 MCS is enabled, fpr PCB REV02 MCS is disabled by default VIO)
  • Monitoring:
    • Set radix from VIO signals (fm_si...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design PCB
Note: REV01 has SI5338 programming default enabled and REV02 default disabled. SI5338 of REV02 is preprogrammed


Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constraints

set_property PACKAGE_PIN AD28 [get_ports sc0841_interface_ddr4_par_44]
set_property PACKAGE_PIN C28 [get_ports sc0841_interface_ddr4_par_46]
set_property PACKAGE_PIN AD20 [get_ports sc0841_interface_en_ddr4pwr]
set_property PACKAGE_PIN AH23 [get_ports sc0841_interface_en_gtpwr]
set_property PACKAGE_PIN AF24 [get_ports sc0841_interface_en_osc]
set_property PACKAGE_PIN AB20 [get_ports sc0841_interface_pll_scl_io]
set_property PACKAGE_PIN P28 [get_ports sc0841_interface_xio_io]
set_property PACKAGE_PIN AE20 [get_ports sc0841_interface_pg_ddr]
set_property PACKAGE_PIN AH22 [get_ports sc0841_interface_pg_gt]
set_property PACKAGE_PIN AB19 [get_ports sc0841_interface_pll_sda_io]

set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_44]
set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_46]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_ddr4pwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_gtpwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_osc]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports sc0841_interface_xio_io]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_ddr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_gt]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_sda_io]

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

create_clock -period 4.950 -name ddr4_0_clk [get_pins */ddr4_b44/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -period 4.950 -name ddr4_1_clk [get_pins */ddr4_b46/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000

create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift {6.700 6.700 6.700} [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier {*STARTUP*_inst/DO[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier {*STARTUP*_inst/DTS[*]}] 1.000
current_instance msys_i/ddr4_b46/inst
set_property LOC MMCME3_ADV_X0Y2 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]
current_instance -quiet
current_instance msys_i/ddr4_b44/inst
set_property LOC MMCME3_ADV_X0Y0 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]

current_instance -quiet
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/util_ds_buf_6/U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/util_ds_buf_5/U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


MCS Firmware to configure SI5338 and Reset System.


TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR.

Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.


  • Modified Files: bootloader.c
  • Changes:
    • Change the SPI defines in the header
    • Add some reiteration in the frist spi read call


Hello TE0841 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description






      • (with this kernel flash address is 0xB00000 (fpga+boot+bootenv) and Kernel size 0xB00000)


Start with petalinux-config -c u-boot


  • No changes.

Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:

#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000  

Device Tree

Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:

/include/ "system-conf.dtsi"
/ {


Start with petalinux-config -c kernel


  • No changes.


Start with petalinux-config -c rootfs


  • # CONFIG_dropbear is not set
  • # CONFIG_dropbear-dev is not set
  • # CONFIG_dropbear-dbg is not set
  • # CONFIG_packagegroup-core-ssh-dropbear is not set
  • # CONFIG_packagegroup-core-ssh-dropbear-dev is not set
  • # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
  • # CONFIG_imagefeature-ssh-server-dropbear is not set


No additional application.

Additional Software


File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

App. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

DateDocument Revision



  • new document style
  • 21.2 release
2020-05-13v.8John Hartfiel
  • 19.2 release
2018-08-07v.7John Hartfiel
  • some notes
2018-06-21v.5John Hartfiel
  • Design update
  • new assembly variants (PCB REV02
2018-06-21v.3John Hartfiel
  • Release 2017.4
  • Initial release
Document change history.

Legal Notices

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Please also note our data protection declaration at

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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