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The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip) including a Cortex-M3 and FPGA Fabric with . The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, four PMODs, a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combiens a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM and a 12 kLUT FPGA Core Logic.
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Table 2: General overview of I/O signals connected to the SoC.
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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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PMODs
The module provides four 2x6 female pin header. Two of the headers are arranged to use as double PMOD. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.
Further I/Os are provided via the PMOD connectors descriebed below.
PMODs
The module provides four 2x6 female PMOD connectors. Two of the headers (P1 and P2) are arranged to use as dual 12 pin PMOD. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.
FPGA SoC Signal | Pin | Label | PMOD Pin / Signal |
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MSIO71PB7 | U2-F3 | P1 | PB-01 |
MSIO71NB7 | U2-F4 | P1 | PB-02 |
MSIO68NB7 | U2-E3 | P1 | PB-03 |
MSIO80NB7 | U2-H4 | P1 | PB-04 |
MSIO75PB7 | U2-G4 | P1 | PB-05 |
MSIO70PB7 | U2-E1 | P1 | PB-06 |
MSIO67NB7 | U2-E5 | P1 | PB-07 |
MSIO78NB7 | U2-G3 | P1 | PB-08 |
MSIO79PB7 | U2-G1 | P2 | PC-01 |
MSIO79NB7 | U2-F1 | P2 | PC-02 |
MSIO70NB7 | U2-E2 | P2 | PC-03 |
MSIO64PB7 | U2-C1 | P2 | PC-04 |
MSIO78PB7 | U2-G2 | P2 | PC-05 |
MSIO70PB7 | U2-E1 | P2 | PC-06 |
MSIO68PB7 | U2-D2 | P2 | PC-07 |
MSIO64NB7 | U2-C2 | P2 | PC-08 |
MSIO117NB4 | U2-Y16 | P3 |
FPGA SoC Signal | Pin | Label | PMOD Pin |
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MSIO117NB4 | U2-Y16 | P1 | PA-01 |
MSIO117PB4 | U2-Y15 | P1 | PA-02 |
MSIO112PB4 | U2-W13 | P1 | PA-03 |
MSIO110PB4 | U2-V12 | P1 | PA-04 |
MSIO118PB4 | U2-W15 | P1 | PA-05 |
MSIO112NB4 | U2-W14 | P1 | PA-06 |
MSIO105NB4 | U2-Y13 | P1 | PA-07 |
MSIO117NB4 | U2-Y16 | P2P2P2P2P2P2P2MSIO117NB4Y1601MSIO117PB4Y15P3PA02MSIO112PB4W13P3PA03MSIO110PB4V12P3PA04MSIO118PB4W15P3PA05MSIO112NB4W14P3PA06MSIO105NB4Y13P3PA07MSIO117NB4Y16PA01MSIO117PB4Y15PA02MSIO112PB4 | U2-W13 | P4 | PA-03 |
MSIO110PB4 | U2-V12 | P4 | PA-04 |
MSIO118PB4 | U2-W15 | P4 | PA-05 |
MSIO112NB4 | U2-W14 | P4 | PA-06 |
MSIO105NB4 | U2-Y13 | P4 | PA-07 |
JTAG Interface
JTAG access to the ... is provided through
JTAG Interface
JTAG access to the SoC components is provided through the micro usb connector via the FTDI usb to UART bridge. Depending on the jumper J6 the JTAGSEL signal SW3 switches the JTAG interface to either the FPGA fabric TAP (open, high) or the Cortex-M3 JTAG debug interface (closed, low).
FTDI signal | pin | JTAG Signal | Microsemi SmartFusion2 SoC FPGA pin |
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ADBUS0 | U3-12 | TCK | U2-W19 |
ADBUS1 | U3-13 | TDI | U2-V16 |
ADBUS2 | U3-14 | TDO | U2-Y20 |
ADBUS3 | U3-15 | TMS | U2-V17 |
JTAG Signal | TCK | JMx-xx |
TDI | JMx-xx |
TDO | JMx-xx |
TMS | JMx-xxTable 5: JTAG interface signals.
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