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Table of Contents

Overview

  


The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip). The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, four Pmods, a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combines a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM  and a 12 kLUT FPGA core logic.

Key Features

  • Microsemi SmartFusion2 SoC FPGA (M2S010)
  • 128 MByte DDR3 SDRAM
  • On board power converters for all needed voltages
  • 40 pin header (compatible to Raspberry Pi pinout)
  • 4 x 12 pin Pmods
  • Gigabit Ethernet PHY with RGMII interface
  • JTAG and UART via Micro USB
  • 3 pin header for Live Probes
  • 2 x User Button
  • 2 x status LED
  • 1 x  RGB LED


Additional assembly options are available for cost or performance optimization upon request.


Block Diagram

Figure 1: TEM0002-01 block diagram.

Main Components


Figure 2: TEM0002-01 main components.
  1. Microsemi SmartFusion2 SoC FPGA, U2
  2. USB to UART/FIFO (FTDI FT2232H), U3
  3. Gigabit ETH connector, J2
  4. 4x  2x6 pin Pmod, P1, P2, P3, P4
  5. GPIO pin header compatible to Raspberry Pi, J8
  6. Micro USB 2.0, J1
  7. EEPROM 4KBIT (M93C66-R), U6
  8. 2x User Button, S4, S5
  9. RGB LED, D3
  10. LED red, D1 and green, D2
  11. Live Probe pins, J4
  12. Reset jumper, J13
  13. JTAG select jumper, J6
  14. Board power header, J5
  15. 1Gb DDR3/L SDRAM, U5
  16. MicroSD memory card connector, J3
  17. Gigabit Ethernet PHY, U1

Initial Delivery State

Storage device name

Content

Notes

Microsemi SmartFusion2 SoC FPGA, U2

Demo Design

-
EEPROM, U6ProgrammedFTDI  (FT2232H) configuration data.

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The SmartBerry supports configuration of the system via JTAG by the FTDI USB bridge.

Signals, Interfaces and Pins

I/Os

26 I/O signals provided on the Rasperry Pi compatible header are connected  to banks with 3.3V. Dpending on the configuration of the SoC, also GPIOs of the Microprocessor subsystem can be routet to the SoC Pins.

FPGA SoC SignalSOC PinHeader PinRaspberry Pi Signal
MSIO19PB2U2-H163GPIO2
MSIO16PB2U2-J175GPIO3
MSIO2PB2U2-T187GPIO4
MSIO1PB2U2-U188GPIO14
MSIO5NB2U2-R1810GPIO15
MSIO11NB2U2-M1711GPIO17
MSIO6PB2U2-P1812GPIO18
MSIO14PB2U2-L1513GPIO27
MSIO17PB2U2-K1615GPIO22
MSIO11PB2U2-N1616GPIO23
MSIO27NB1U2-B1918GPIO24
MSIO25NB1U2-C2019GPIO10
MSIO25PB1U2-D2021GPIO9
MSIO22NB1U2-F1822GPIO25
MSIO20NB2U2-F2023GPIO11
MSIO20PB2U2-G1924GPIO08
MSIO18PB2U2-H1926GPIO07
MSIO28PB1U2-A2027ID_SDA
MSIO28NB1U2-A1928ID_SCL
MSIO16NB2U2-J1829GPIO05
MSIO15NB2U2-J2031GPIO06
MSIO15PB2U2-K2032GPIO12
MSIO14NB2U2-L1633GPIO13
MSIO13NB2U2-L1935GPIO19
MSIO13PB2U2-L2036GPIO16
MSIO8PB2U2-N2037GPIO26
MSIO8NB2U2-M1938GPIO20
MSIO4NB2U2-N1940GPIO21

Table 2: General overview of I/O signals connected to the SoC.

Further I/Os are provided via the Pmod connectors descriebed below.

Pmods

The module provides four 2x6 female Pmod connectors. Two of the headers (P2 and P3) are arranged to use as dual 12 pin Pmod. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.

FPGA SoC SignalPin

Pmod  Signal

Pmod Pin
MSIO71PB7U2-F3PB-01P1-1
MSIO71NB7U2-F4PB-02P1-2
MSIO68NB7U2-E3PB-03P1-3
MSIO80NB7U2-H4PB-04P1-4
MSIO75PB7U2-G4PB-05P1-7
MSIO75NB7U2-F5PB-06P1-8
MSIO67NB7U2-E5PB-07P1-9
MSIO78NB7U2-G3

PB-08

P1-10
MSIO79PB7U2-G1PC-01

P2-1

MSIO79NB7U2-F1PC-02P2-2
MSIO70NB7U2-E2PC-03P2-3
MSIO64PB7U2-C1PC-04P2-4
MSIO78PB7U2-G2PC-05P2-7
MSIO70PB7U2-E1PC-06P2-8
MSIO68PB7U2-D2

PC-07

P2-9
MSIO64NB7U2-C2

PC-08

P2-10
MSIO117NB4U2-Y16PA-01P3-1
MSIO117PB4U2-Y15PA-02P3-2
MSIO112PB4U2-W13PA-03P3-3
MSIO110PB4U2-V12PA-04P3-4
MSIO118PB4U2-W15PA-05P3-7
MSIO112NB4U2-W14PA-06P3-8
MSIO105NB4U2-Y13PA-07P3-9
MSIO104PB4U2-V11PA-08P3-10
MSIO4PB2U2-P20PD-01P4-1
MSIO3NB2U2-R20PD-02P4-2
MSIO2NB2U2-T19PD-03P4-3
MSIO0PB2U2-V20PD-04P4-4
MSIO6NB2U2-P19PD-05P4-7
MSIO3PB2U2-T20PD-06P4-8
MSIO1NB2U2-U19PD-07P4-9
MSIO0NB2U2-V19PD-08P4-10

Table 3: Overview of Pmod signals connected to the SoC.

JTAG Interface

JTAG access to the SoC components is provided through the micro usb connector via the FTDI usb to UART bridge. Depending on the jumper J6 the JTAGSEL signal SW3 switches the JTAG interface to either the FPGA fabric TAP (OPEN, high) or the Cortex-M3 JTAG debug interface (CLOSED, low). JTAG signals are powered by 3.3V.

FTDI signal

pin

JTAG Signal

Microsemi SmartFusion2 SoC pin

ADBUS0U3-12TCKU2-W19
ADBUS1U3-13TDIU2-V16
ADBUS2U3-14TDOU2-Y20
ADBUS3U3-15TMSU2-V17

Table 4: JTAG interface signals.

SD Card Interface

The SD Card interface is connected to bank 2 of the SoC

FPGA / SoC PinConnected ToSignal NameNotes
U2-H16J3-9SD_CDCard detect switch
U2-N15J3-7SD_D0
U2-G18J3-8SD_D1
U2-R16J3-1SD_D2
U2-R17J3-2SD_D3
U2-R15J3-3SD_CMD
U2-P15J3-5SD_CLK

Table 5: SD Card interface signals and connections.

Ethernet Interface

PHY PinSignalMicrosemi SmartFusion2 SoC signalPinNotes
U1-25ETH_TXCKMSIOD84PB6U2-K7
U1-23

ETH_TXCTL

MSIOD87NB6U2-K3
U1-26ETH_TXD0MSIOD93PB6U2-L1
U1-28ETH_TXD1MSIOD97NB6U2-M2
U1-29ETH_TXD2MSIOD97PB6U2-M1
U1-30ETH_TXD3MSIOD95PB6U2-M3
U1-22ETH_RRXCKMSIOD84PB6U2-J2
U1-21ETH_RRXCTLMSIOD93NB6U2-K1
U1-20ETH_RRXD0MSIOD86PB6U2-K5

U1-18

ETH_RRXD1MSIOD82PB6

U2-H1


U1-17ETH_RRXD2MSIOD82NB6U2-H2
U1-16ETH_RRXD3MSIOD83PB6U2-J4
U1-31ETH_MDCMSIOD99PB6U2-N1
U1-33ETH_MDIOMSIOD99NB6U2-N2
U1-34

ETH_MDINT

MSIOD98PB6U2-N4
U1-35ETH_RSTMSIO114PB4U2-R13
U1-36PHY_RCLKOUTMSIO102NB4/CCC_NE1_CLKIOU2-W10
U1-39PHY_LED0MSIO104NB4U2-U11
U1-38PHY_LED1MSIO116PB4U2_T14

Table 6: Ethernet PHY signals and connections.

I2C Interface

There are no on-board I2C devices.  For Raspberry Pi compability the device detection I2C bus is routed from the header J8-27/28 to Bank 1 U2-A20/A19 (SDA/SCL). 

I2C DeviceI2C AddressNotes
Header J80x50Device detection/identification.

Table 7: I2C slave device addresses.

On-board Peripherals

DDR Memory

TEM0002 has 1Gb industrial grade DDR3 SDRAM (U5). A 16-bit wide memory bus providing total of 128 MBytes of on-board RAM. Specification is 800 MHz clocking resulting in 1600 Mb/s data rate and timings  of 11-11-11 (CL-TRCD-TRP).

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (J2) is provided by  Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Clock SourceSchematic NameFrequencyClock Destination
Crystal CX3225CA25000D0HSSCCY1

25.000 MHz1

SmartFusion2 SoC U2 Main XTAL
Crystal ECX-31BY232.768 KHzSmartFusion2 SoC U2 AUX XTAL
SiTime SiT8008AI oscillatorU1125.000000 MHzGb Ethernet Copper PHY U1A
SiTime SiT8008AI oscillatorU1425.000000 MHz

SmartFusion2 SoC U2-Y12 Bank 4

Table 8: Reference clock signals.

1In REV02, Y1 will be replaced by a 12 MHz crystal.

On-board LEDs

LED ColorConnected toSoC FPGA SignalDescription and Notes
D1RedU2-G16 Bank 1MSIO21PB1
D2GreenU2-G17 Bank 1MSIO21NB1
D3RGB

U2-H5 Bank 7, U2-F6 Bank 7, U2-H6 Bank 7

MSIO80PB7, MSIO67PB7, MSIO81NB7
J2Green, YellowU2-Y10 Bank 4, U2-U12 Bank 4MSIO102PB4, MSIO110NB4Ethernet: LED1A, LED1B
J2Green, YellowU2-V14 Bank 4, U2-U14 Bank 4MSIO115PB4, MSIO115PB4Ethernet: LED2A, LED2B

Table 9: On-board LEDs.

On-board Buttons

ButtonConnected toSoC FPGA Signal
S4U2-E17 Bank 1MSIO24PB1
S5U2-E16 Bank 1MSIO24NB1

Table 10: On-board Buttons.

Power and Power-On Sequence

There is no specific power on Sequence. Just supply with 5V via the micro USB J1 or the J5 PWR_IN with current rating sufficient for your Design.

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Power InputTypical Current
VINTBD*
3.3VINTBD*

Table 11: Typical power consumption.


 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

Figure 3: Module power distribution diagram.


Power Rails

Power Rail Name

Connector pin

Direction

Notes
VINJ5-1InputMain supply voltage.
5VJ8-2, J8-4Output
3.3VJ8-1, J8-17Output
1.5V-Output

1.2V

-Output
GNDJ5-2, J8-9/25/39/6/14/20/30/34

Table 12: Module power rails.

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

0 (DDR3)1.5V 1.5V-
13.3V3.3V-
23.3V3.3V-
33.3V3.3V-
43.3V3.3V-
5

1.5V

1.5V

-
6

1.5V

1.5V-
73.3V3.3V-

Table 13:  I/O bank voltages.

Variants Currently In Production

 Module VariantFPGA / SoC

Operating Temperature

Temperature Range
TEM0002-01M2S0100°C to +70°Ccommercial

Table 14: Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.36.0

V

-

Storage temperature1

-25

70

°C

-

Table 15: Module absolute maximum ratings.

1Boundary determined by the specification of the buttons, all other components have at least a range of -40°C to  85°C.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage2.45.5V-
Operating temperature1070°C-

Table 16: Module recommended operating conditions.

1Upper bound is determined by the buttons, all other components have at least a upper bound of 85 °C.

Operating Temperature Ranges

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 85 mm × 56 mm.  Please download the assembly diagram for exact numbers.

  • PCB thickness: 1.55 mm.

  • Highest part on PCB: top approx. 13.3 mm (Ethernet), bottom 1.57mm (SD-Card)Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 4: Module physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes



Table 17: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


Figure 5: Module hardware revision number.

Document Change History


Date

Revision

Contributors

Description

  • initial document

all

Jan Kumann, John Hartfiel


Table 18: Document change history.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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