Page History
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Date | Vivado | Project Built | Authors | Description |
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2018.05.24 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip | John Hartfiel |
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2018-02-06 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip | John Hartfiel |
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2018-02-05 | 2017.4 | TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip | John Hartfiel |
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2018-01-18 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip | John Hartfiel |
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Issues | Description | Workaround/Solution | To be fixed version |
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Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”"next design | Solved with 20180524 update |
USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is nessecary:
| Solved with 20180205 update |
Requirements
Software
HTML |
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<!-- Add needed external Software --> |
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Code Block | ||||
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#LED_HD SC0 J3:31
set_property PACKAGE_PIN K11 [get_ports {LED_HD[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_HD[0]}]
#LED_XMOD SC17 J3:48
set_property PACKAGE_PIN B12 [get_ports {LED_XMOD2[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_XMOD2[0]}]
#System Controller IP
#J3:32
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
#J3:34
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
#J3:36
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
#J3:38
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
#J3:40
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
#J3:42
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:41
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
#J3:45
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
#J3:47
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
# PLL
#J4:74
#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Audio Codec
#LRCLK J3:49 B47_L9_N
set_property PACKAGE_PIN G14 [get_ports LRCLK ]
#BCLK J3:51 B47_L9_P
set_property PACKAGE_PIN H14 [get_ports BCLK ]
#DAC_SDATA J3:53 B47_L7_N
set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
#ADC_SDATA J3:55 B47_L7_P
set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
# CAN
#CAN RX SC19 J3:52 B47_L10_P
#CAN TX SC18 J3:50 B47_L10_N
#CAN S SC16 J3:46 B47_L12_N
set_property PACKAGE_PIN A12 [get_ports CAN_0_S ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_S ]
set_property PACKAGE_PIN C14 [get_ports CAN_0_rx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_rx ]
set_property PACKAGE_PIN B14 [get_ports CAN_0_tx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ]
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Code Block | ||
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/include/ "system-conf.dtsi" / { }; /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { // compatible = "n25q256ajedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_2: clock-generator3@5d { #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <78800000>; }; }; i2c@7 { // i2c USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // i2c PMOD #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // i2c FireFly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c FireFly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c PLL #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c SC #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* UNUSED DMA disable */ &lpd_dma_chan1 { status = "disabled"; }; &lpd_dma_chan2 { status = "disabled"; }; &lpd_dma_chan3 { status = "disabled"; }; &lpd_dma_chan4 { status = "disabled"; }; &lpd_dma_chan5 { status = "disabled"; }; &lpd_dma_chan6 { status = "disabled"; }; &lpd_dma_chan7 { status = "disabled"; }; &lpd_dma_chan8 { status = "disabled"; }; |
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v.10 | John Hartfiel |
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v.9 | John Hartfiel |
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2018-01-29 | v.4 | John Hartfiel |
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2018-01-18 | v.3 | John Hartfiel |
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