Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).

Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2022.2
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • Display Port (DP)
  • user LED access
  • Modified FSBL for Si5345 programming / petalinux patch

Revision History

DateVivadoProject BuiltAuthorsDescription
Manuela Strücker
  • 2022.2 update
  • new assembly variants
Manuela Strücker
  • script update
Manuela Strücker
  • update board part file compatible to Vivado 2021.2.1
Manuela Strücker
  • 2021.2 update
  • new assembly variants
  • update document style
John Hartfiel
  • 2020.2 update
  • add boot.scr file
  • device tree has change
  • petalinux fsbl patch (betaversion)
John Hartfiel
  • new assembly variants
John Hartfiel
  • script update
John Hartfiel
  • add missing linux Boot.bin
  • small update for  SI configuration (FSBL)
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
  • ES2 prebuilt files are not included
John Hartfiel
  • new assembly variant
John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
John Hartfiel
  • solved Linux Flash issue
John Hartfiel
  • same CLK for VIO
John Hartfiel
  • solved JTAG/Linux issue
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaround/SolutionTo be fixed version
Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--

The MAC address stored in the EEPROM is not read out and initialised correctly during start-up.
This is caused by two I2C expanders each switched to the same EEPROM with the same address
i2cswitch@73 --> i2c@5 --> reg = <0x50> and
i2cswitch@77 --> i2c@4 --> reg = <0x50>

Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.

with update

QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
If flash programming fails, configure device for JTAG boot mode and try again or use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update
Known Issues



Vitis2022.2needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   es2_2gb      REV01    2GB      64MB       NA         NA     Not longer supported by vivado
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      128MB     NA         NA     NA                               
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-4BE21-A   4eg_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DE21-A   7ev_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI21-C   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     without encryption             
TE0807-02-7DI21-A   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-4AI21-X   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     U41 replaced with diode        
TE0807-02-4BE21-AK  4eg_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-7DI21-AK   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
TE0807-02-5DI21-A   5ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7NE21-A   7ev_3e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-03-5DI21-A   5ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7NE21-A   7ev_3e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-4AI21-X   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     U41 replaced with diode        
TE0807-03-4AI21-A   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-4AI21-C   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
TE0807-03-4BE21-A   4eg_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-5AI21-A   5cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7AI21-A   7cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DE21-A*  7ev_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DE21-AK  7ev_1e_4gb   REV03    4GB      128MB      NA         NA     with heat sink                 
TE0807-03-7DI21-A   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
TE0807-03-7DI21-C   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
TE0807-03-7DI24-A   7ev_1i_4gb   REV03    4GB      512MB      NA         NA     NA    
TE0807-03-4BE21-AK4eg_1e_4gbREV034GB128MBNA NA NA 
TE0807-03-S0087ev_1i_me_8gbREV038GB128MBNAwithout PLLCAO Micron DDR
TE0807-03-S0117ev_1i_me_8gbREV038GB128MBNAwithout PLLCAO Micron DDR

*used as reference

Hardware Modules

Note: Design contains also Board Part Files for TE0807 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Carrier ModelNotes
TEBF0808*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
Display Port Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was testet with  DELL U2412M

USB KeyboardOptional HW
Can be used to get access to console which is show on Display Port
USB StickOptional HW
USB was tested with USB memory stick
SATA DiskOptional HW
PCIe CardOptional HW
ETH cableOptional HW
Ethernet works with DHCP, but can be setup also manually
SD cardwith fat32 partition

*used as reference

Additional Hardware


For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

SI5345<project folder>\misc\PLL\Si5345_BSI5345 Project with current PLL Configuration
init.sh<project folder>\misc\sdAdditional initialization script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

      Important: Use Board Part Files, which ends with *_tebf0808

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Generate Programming Files with Vitis
    1. Copy PetaLinux build image files to prebuilt folder
      • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
    2. Generate Programming Files

      run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

  8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart


For basic board setup, LEDs... see: TEBF0808 Getting Started


Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0807
  3. Set Boot Mode to QSPI-Boot
    • Depends on Carrier, see carrier TRM.
    • TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

SD-Boot mode

  1. Copy image.ub, boot.scr and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  5. (Optional with TEBF0808) Connect SATA Disc
  6. (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  7. (Optional with TEBF0808) Connect Network Cable
  8. Power On PCB

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    # password disabled
    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 0 Bus, replace 0 with other bus number is also possible)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
    lspci               (PCIe check)
  4. Option Features

    • Webserver to get access to ZynqMP
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado Hardware Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
  • Control:
    • LEDs: XMOD 2(without green dot) and HD LED are accessible.
    • CAN_S

Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

PS Interfaces


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

#System Controller IP

#J3:31 LED_HD
set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
#J3:46 CAN S
set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
#J3:50 CAN TX 
set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
#J3:52 CAN RX 
set_property PACKAGE_PIN C14 [get_ports BASE_sc19]

set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

#set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]

# Audio Codec
#LRCLK		J3:49 B47_L9_N
#BCLK		J3:51 B47_L9_P
#DAC_SDATA	J3:53 B47_L7_N
#ADC_SDATA	J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN H14 [get_ports I2S_bclk ]
set_property PACKAGE_PIN C13 [get_ports I2S_sdin ]
set_property PACKAGE_PIN D14 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

# MGTs
#   R8    MGT_224_CLK0_P -> B2B,J3-62 -> TEBF0808-04a_FMC_J5E-D5
#   R7    MGT_224_CLK0_N -> B2B,J3-60 -> TEBF0808-04a_FMC_J5E-D4
#   N8    MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
#   N7    MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4

#   L8    MGT_225_CLK0_P -> B2B,J3-67 -> TEBF0808-04a_FMC_J5E-B21
#   L7    MGT_225_CLK0_N -> B2B,J3-65 -> TEBF0808-04a_FMC_J5E-B20
#   J8    MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
#   J7    MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3

#   H10   MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
#   H9    MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
#   F10   MGT_226_CLK1_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> U5,51 -> Si5345 -> out7
#   F9    MGT_226_CLK1_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> U5,50 -> Si5345 -> out7

#   D10   MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
#   D9    MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
#   B10   MGT_227_CLK1_P -> B2B,J2-22 -> floating
#   B9    MGT_227_CLK1_N -> B2B,J2-24 -> floating

set_property PACKAGE_PIN R8   [get_ports {MGT_CLK_IN_clk_p[0]}]
set_property PACKAGE_PIN N8   [get_ports {MGT_CLK_IN_clk_p[1]}]
set_property PACKAGE_PIN L8   [get_ports {MGT_CLK_IN_clk_p[2]}]
set_property PACKAGE_PIN J8   [get_ports {MGT_CLK_IN_clk_p[3]}]
set_property PACKAGE_PIN H10  [get_ports {MGT_CLK_IN_clk_p[4]}]
set_property PACKAGE_PIN F10  [get_ports {MGT_CLK_IN_clk_p[5]}]
set_property PACKAGE_PIN D10  [get_ports {MGT_CLK_IN_clk_p[6]}]
set_property PACKAGE_PIN B10  [get_ports {MGT_CLK_IN_clk_p[7]}]

# MGTs
#   R8    MGT_224_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5
#   R7    MGT_224_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4
#   N8    MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
#   N7    MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4

#   L8    MGT_225_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21
#   L7    MGT_225_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20
#   J8    MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
#   J7    MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3

#   H10   MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
#   H9    MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
#   F10   MGT_226_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7
#   F9    MGT_226_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7

#   D10   MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
#   D9    MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
#   B10   MGT_227_CLK1_P -> B2B,J2-A6 -> floating
#   B9    MGT_227_CLK1_N -> B2B,J2-A7 -> floating

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


TE modified 2022.2 FSBL


  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5345 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC


Xilinx default PMU firmware.


Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description


  • select SD default instead of eMMC:
  • add new flash partition for bootscr and sizing
  • Identification


Start with petalinux-config -c u-boot


  • MAC from eeprom together with uboot and device tree settings:
    • CONFIG_ZYNQ_MAC_IN_EEPROM is not set
  • Boot Modes:
    • CONFIG_ENV_IS_IN_FAT is not set
    • CONFIG_ENV_IS_IN_NAND is not set
    • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • Identification

Change platform-top.h:

#no changes

Device Tree

/include/ "system-conf.dtsi"

/*------------------ gtr --------------------*/


/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;

  refclk2:psgtr_pcie_usb_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <100000000>;

  refclk1:psgtr_sata_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <150000000>;

  //refclk0:psgtr_unused_clock {
  //        compatible = "fixed-clock";
  //        #clock-cells = <0x00>;
  //        clock-frequency = <100000000>;

&psgtr {
  clocks = <&refclk1 &refclk2 &refclk3>;
  /* ref clk instances used per lane */
  clock-names = "ref1\0ref2\0ref3";

/*------------------ SD --------------------*/
&sdhci0 {
    // disable-wp;


&sdhci1 {
    // disable-wp;


/*------------------- USB --------------------*/
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    phy-names = "usb2-phy","usb3-phy";
    maximum-speed = "super-speed";

/*------------------ ETH PHY --------------------*/
&gem3 {
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;

/*----------------- SATA PHY --------------------*/
&sata {

			ceva,p0-burst-params = <0x13084a06>;
			ceva,p0-cominit-params = <0x18401828>;
			ceva,p0-comwake-params = <0x614080e>;
			ceva,p0-retry-params = <0x96a43ffc>;
			ceva,p1-burst-params = <0x13084a06>;
			ceva,p1-cominit-params = <0x18401828>;
			ceva,p1-comwake-params = <0x614080e>;
			ceva,p1-retry-params = <0x96a43ffc>;


/*-------------------- QSPI ---------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

/*------------------ I2C --------------------*/
&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            reg = <0>;
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            reg = <1>;
        i2c@2 { // PCIe
            reg = <2>;
        i2c@3 { // SFP1 TEBF0808
            reg = <3>;
        i2c@4 {// SFP2 TEBF0808
            reg = <4>;
        i2c@5 { // TEBF0808 EEPROM
            reg = <5>;
            eeprom: eeprom@50 {
                compatible = "microchip,24aa025", "atmel,24c02";
                reg = <0x50>;
                #address-cells = <1>;
                #size-cells = <1>;
                eth0_addr: eth-mac-addr@FA {
                  reg = <0xFA 0x06>;
        i2c@6 { // TEBF0808 FMC
            reg = <6>;
        i2c@7 { // TEBF0808 USB HUB
            reg = <7>;
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        reg = <0x77>;
        i2c@0 { // TEBF0808 PMOD P1
            reg = <0>;
        i2c@1 { // i2c Audio Codec
            reg = <1>;
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
        i2c@2 { // TEBF0808 Firefly A
            reg = <2>;
        i2c@3 { // TEBF0808 Firefly B
            reg = <3>;
        i2c@4 { //Module PLL Si5338 or SI5345
            reg = <4>;
        i2c@5 { //TEBF0808 CPLD
            reg = <5>;
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            reg = <6>;
        i2c@7 { // TEBF0808 PMOD P3
            reg = <7>;


Start with petalinux-config -c kernel


  • Only needed to fix JTAG Debug issue:
    • # CONFIG_CPU_IDLE is not set
    • # CONFIG_CPU_FREQ is not set
  • Support PCIe memory card
    • # CONFIG_NVME_MULTIPATH is not set
    • # CONFIG_NVME_HWMON is not set
    • # CONFIG_NVME_TCP is not set
    • # CONFIG_NVME_TARGET_LOOP is not set
    • # CONFIG_NVME_TARGET_FC is not set
    • # CONFIG_NVME_TARGET_TCP is not set


Start with petalinux-config -c rootfs


  • For web server app:
    • CONFIG_busybox-httpd=y
  • For additional test tools only:
    • CONFIG_i2c-tools=y
    • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • For auto login:
    • CONFIG_auto-login=y
    • CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"


See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"


Script App to load init.sh from SD Card if available.


Webserver application suitable for ZynqMP access. Need busybox-httpd

Additional Software


File location "<project folder>\misc\PLL\Si5345_B\Si5345-*.slabtimeproj"

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument Revision



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Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy279.$Proxy4022#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

  • 2022.2 update
  • new assembly variants
2022-10-17v.27Manuela Strücker
  • script update
2022-09-12v.26Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
2022-09-12v.25Manuela Strücker
  • 2021.2 update
  • new assembly variants
  • update document style
2021-05-11v.23Martin Rohrmüller
  • 2020.2 release
  • document style update
2020-10-06v.21John Hartfiel
  • new assembly variants
2020-03-25v.20John Hartfiel
  • script update
2020-02-25v.19John Hartfiel
  • Update requirement section
2020-02-19v.18John Hartfiel
  • Design update
2020-01-27v.17John Hartfiel
  • new assembly variants
  • Release 2019.2
2019-05-22v.16John Hartfiel
  • Release 2018.3


v.13John Hartfiel
  • Release 2018.2


v.12John Hartfiel
  • Design update


v.10John Hartfiel
  • Update known issues


v.9John Hartfiel
  • Design update
2018-01-29v.4John Hartfiel
  • Update known issues
2018-01-18v.3John Hartfiel
  • Release 2017.4


Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy279.$Proxy4022#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

Document change history.

Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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Error rendering macro 'page-info'

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