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Additional assembly options are available for cost or performance optimization upon request.
Block Diagramm
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Main Components
draw.io Diagram border false viewerToolbar true fitWindow false diagramName TE0724-02_Top simpleViewer true width links auto tbstyle top lbox true diagramWidth 641 revision 2 draw.io Diagram border false viewerToolbar true fitWindow false diagramName TE0724-02_Bottom simpleViewer true width links auto tbstyle top lbox true diagramWidth 641 revision 3
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Storage device name | Content | Notes |
|---|---|---|
| Spansion SPI Flash S25FL256, U13 | Empty? | |
| DA9062, U4 | Programmed | |
| Microchip 24AA128T, U10 | Empty | USER EEPROM |
| Microchip 24AA025E48T, U23 | Empty | EEPROM for MAC-Address. |
| TPS3106K33DBVR, U26 | Empty | Required for Zynq eFUSE (ERRATA ADDENDUM) |
Table 1: Initial delivery state of Table 1: Initial delivery state of programmable devices on the module.
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Boot mode is selected via two pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins 40 to 45 or MIO 46 to 51 gives the possibility to boot from SD Card.
Boot mode | MODE1 J1-2 | MODE0 J1-4 |
|---|---|---|
| JTAG (cascade) | LOW | LOW |
| invalid | LOW | HIGH |
| SPI | HIGH | LOW |
| SD CARD (not on module) | HIGH | HIGH |
Table 2: Boot mode selection.
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Table 4: JTAG interface signals.
System Controller
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Pins
Special purpose pins are connected to smaller available for System Controller CPLD functions and have following default configuration:
Pin
Default
PGOOD
Output
Power Good
148Active high when all on-module power supplies are working properly. JTAGEN Input JTAG Select J2-131 Low for normal operation. .. .. .. .. ..
| Signal Name | Mode | Function | B2B Connector Pin |
|---|
| Configuration |
|---|
| RESETREQ |
| INPUT |
| Reset request | J1- |
| 150 | Aktive LOW, enter reset mode when set low. Pulled up to VIN. | |||
| ONKEY | INPUT | Power-on key | J1-148 | Debounced edge sensitve power mode manipulator. On/Off with optional long press shutdown, function dependent on register value of NONKEY_PIN, KEY_DELAY. |
| PWR_TP | IN/OUT | Test pin | J1-146 | Enables Power Commander boot mode and supply pin for OTP fusing voltage. |
| PWR_GPIO2 | IN/OUT | J1-143 | ||
| PWR_GPIO2 | IN/OUT | J1-141 | ||
| PGOOD | Output | Power Good | J1-148 | Active high when all on-module power supplies are working properly. |
| JTAGEN | Input | JTAG Select | J2-131 | Low for normal operation. |
Table Table 5: System Controller CPLD I/O pins.
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Date | Revision | Contributors | Description | ||||||||||||||||
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| John Hartfiel |
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| v.60 | John Hartfiel |
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| 2017-11-10 | v.58 | Ali Naseri |
| 2017-09-06 | v.56 | Jan Kumann | |||||||||||||
| John Hartfiel |
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| v.60 | John Hartfiel |
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2017-09-02 | v.54 | Jan Kumann | DDR Memory section added. | ||||||||||||||||
2017-08-27 | v.43 | John Hartfiel |
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| 2017-08-16 | v.42 | Jan Kumann |
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2017-08-07 | v.32 | Jan Kumann | Few corrections and cosmetic changes. | ||||||||||||||||
2017-07-14 | v.25 | John Hartfiel | Removed weight section update template version | ||||||||||||||||
2017-06-08 | v.20 | John Hartfiel | Add revision number and update document change history | ||||||||||||||||
2017-05-30 | v.1 | Jan Kumann | Initial document. | ||||||||||||||||
all | Jan Kumann, John Hartfiel |
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| Include Page | ||||
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Overview
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