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Table of Contents

Table of Contents

Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TEBA0841+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEBA0841 is a Carrier Board for testing, evaluation and development purposes, especially for the Multi-gigabit transceiver units of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs.

...

The Trenz Electronic TEBA0841 is a low cost carrier board for testing, evaluation and development purposes of the TE0841 and TE0741 modules. Although this base-board is dedicated to the modules TE0841 and TE0741, it is also compatible with other Trenz Electronic 4 x 5 cm SoMs. The carrier board offers one SFP connector, one Micro USB2 B connector, two 2x25-pin headers and one XMOD header to get access to the I/O's and interfaces of FPGA modules. To test and evaluate the Multi-gigabit transceiver units of the FPGA module, 6 MGT lanes on the carrier board are routed in a loop-back circuit on the B2B connectors.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TEBA0841 carrier board.

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Refer to http://trenz.org//teba0841-info for the current online version of this manual and other available documentation.

Key Features

  • SFP+ connector (Enhanced small form-factor pluggable), supports data transmission rates up to 10 Gbit/s
  • Micro USB2 .0 Type B Connector (J10)
  • Trenz Electronic 4x5 module Socket B2B connectors (3 x Samtec LSHM series connectors)
  • 4 x 5 SoM programmable by XMOD JTAG/UART header (JX1)
  • 2 x user LEDs routed to I/O-pins of the SoM
  • Soldering-pads J17 and J20 for optional pin headers for access to SoM's I/O-bank - pins, usable as LVDS-pairs
  • Soldering-pads J3 and J4 for optional pin headers for access to further interfaces and I/O's of the SoM
  • 2 x user LEDs routed to I/O-pins of the SoM
  • 4-bit DIP switch for setting module parameters
  • 4x VCCIO selection jumper to set module's bank voltages

Additional assembly options are available for Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TEBA0841-01 Block Diagram.

Main Components

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Figure 2TEBA0841-01 Carrier Board.

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Main Component

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Photo shows similar TEBA0841-01

  1. Samtec Razor Samtec Razor Beam™ LSHM-150 B2B connector, JB1
  2. Samtec Razor Beam™ LSHM-150 B2B connector, JB3
  3. Samtec Razor Beam™ LSHM-130 B2B connector, JB2
  4. 6-pin header J26, for selecting PL I/O-bank voltage
  5. 6-pin header J27, for selecting PL I/O-bank voltage
  6. Micro USB2 .0 Type B Connector connector J12 (Device or OTG mode)
  7. XMOD FTDI JTAG/UART header, JX1 ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  8. User LED D1 (green)
  9. User LED D2 (red)
  10. SFP+ Connector, J1
  11. 50-pin header soldering-pads J17, for access to PL I/O-bank pins (LVDS-pairs possible42 I/O'S, 21 LVDS pairs)
  12. 50-pin header soldering-pads J20, for access to PL I/O-bank pins (LVDS-pairs possible42 I/O'S, 21 LVDS pairs)
  13. 16-pin header soldering-pads J3, JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible pin-assignment)
  14. 10-pin header soldering-pads J4, for access to SoM6 I/O's SDIO-port, if available

Initial Delivery State

Board is shipped in following configuration:

  • VCCIO voltage selection jumpers are all set to 1.8 V.
  • Pin headers (not soldered to the board, but included in the package as separate component)

...

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Connections and Interfaces or B2B Pin's which are accessible by User
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B2B Connector

With the TEBA0841 Carrier Board's Board-to-Board Connectors (B2B) the MIO- and PL I/O-bank's pins and further interfaces of the mounted SoM can be accessed. A large quantity of these I/O's are also usable as differential pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

-->

B2B Connectors

Following table gives a summary of the available I/O's, interfaces and differential pairs of the mounted SoM on the B2B connectors JB1, JB2 and JB3 of the carrier board:

B2B Connector
InterfacesI/O Signal CountLVDS-pairs countConnected toNotes
JB1I/O42212x25-pin header J20-
6-10-pin header J4-
Control signals5-SFP+ connector J1

'TX FAULT', 'MOD-DEF0' ... 'MOD-DEF2', 'LOS'

4-DIP switch S1'JTAGEN (BOOTMODE)', 'EN1', 'MODE', 'NOSEQ'
1-Green LED D1user LED
UART2-XMOD header JX1, 16-pin header J3also usable as GPIO's
MGT-4 (2 MGT lanes)2x loop back circuit on B2B connector JB1-
JB2USB-1Micro USB2 Type B connector J10-
MGT-2 (1 MGT lanes)SFP+ connector J1-
-8 (4 MGT lanes)4x loop back circuit on B2B connector JB2-
Clock-1MGT clock input from 16-pin header J3-
JB3I/O42212x25-pin header J17-
JTAG4-XMOD header JX1, 16-pin header J3-
Control signals1-XMOD header JX1, 16-pin header J3'RESIN', nRESET signal to mounted SoM
1-Red LED D2user LED
B2B ConnectorInterfacesCount of I/O'sNotesJB1User I/O42 single ended or 21 differential-SD IO6-MIO8-SoM control signals1'BOOTMODE'JB2MGT lanes8 differential pairs, 4 lanes-MGT reference input clock1 differential pairUSB2.0 (OTG and device mode)4-JB2User I/O42 single ended 21 differential--JTAG4-Red user LED1-SoM control signals1'RESIN'

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

On-board Pin Header

The TEBA0841 Carrier Board carrier board has 4 footprints as soldering pads to mount 2.54mm grid size pin headers to get access the PL I/O-bank's pins and further interfaces of the mounted SoM. With these pin headers, SoM's PL-I/O's are available to the user, a large quantity of these I/O's are also usable as  differential pairs.

Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

On-board Pin Header
Control
Signals and InterfacesCount of I/O'sNotes
J17User I/O42 single ended or 21 differential-
J20User
J20

User I/O

42 single ended or 21 differential-
JX1JTAG4-
Control signals1'RESIN'
I/O
42 single ended or 21 differential-
's2user IO (configurable as UART)
J3JTAG4-
SoM control
Control signals
2
1'RESIN'
, 'BOOTMODE'
I/O's2user IO (configurable as UART)
MGT reference input clock1 differential pairAC decoupled on-board (100 nF capacitor)
MIO
2user IO (configurable as UART for example)
J4User I/O6 single ended
J4SD IO6
3.3V and 1.8V voltage level available on header

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

SFP+ Connector

The TEBA0841 Carrier Board carrier board is equipped with one SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded fitted into a SFP cage J2 (board-rev. 01: Molex 74737-0009).

The differential RX/TX data lanes are connected to B2B connector JB2, the control-lines are connected to B2B connector JB1 and are assigned to MIO-pins of the mounted SoMconnector JB1.

Following table describes the pin-assignment of the SFP+ connector in detail:

SFP+ pinPin Schematic NameB2BFPGA DirectionDescriptionNote
Transmit Data + (pin 18)MGT_TX3_PJB2-26OutputSFP+ transmit data differential pair

-
Transmit Data - (pin 19)MGT_TX3_NJB2-28Output-
Receive Data + (pin 13)MGT_RX3_PJB2-25InputSFP+ receive data differential pair

-
Receive Data - (pin 12)MGT_RX3_NJB2-27Input-
Receive Fault (pin 2)MIO10JB1-96InputFault / Normal OperationHigh active logic
Receive disable (pin 3)
1)
SFP0_TX_DISnot connectedOutputSFP Enabled / DisabledLow active logic
MOD-DEF2 (pin 4)MIO13JB1-98BiDir2-wire Serial Interface data3.3V pull-up on-board
MOD-DEF1 (pin 5)MIO12JB1-100Output2-wire Serial Interface clock3.3V pull-up on-board
MOD-DEF0 (pin 6)MIO11JB1-94InputModule present / not presentLow active logic
RS0 (pin 7)SFP0_RS0not connectedOutputFull RX bandwidthLow active logic
LOS (pin 8)MIO0JB1-88InputLoss of receiver signalHigh active logic
RS1 (pin 9)SFP0_RS1not connectedOutputReduced RX bandwidthLow active logic

Table 3: SFP+ connector pin-assignment.

1) Important: For proper operation, a wire patch to GND is done at recently delivered boards. Connect to GND, if not done. See PCB drawing below:

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Figure 3: PCB wire patch for SFP+ connector.

...

Loop Back Circuits on B2B Connector JB1 and JB2

The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their the FPGA -modules devices with up to 8 available MGT - lanes. To test this MGT - lanes, 5 6 RX/TX differential pairs are bridged routed in loop back circuit on-board, hence the transmitted data on this those MGT - lanes flows back to their sources its source in a loop - back circuit without intentional processing or modification.

The MGT lane pins are bridged routed on-board as fellowsfollows, if 4 x 5 SoM TE0741 TE0841 is mounted on carrier board:

MGT LaneB2B TX Differential PairB2B RX Differential PairB2B Pins
Bridged
connected
MGT-lane 0

JB2-8 (MGT_TX0_N)

JB2-10 (MGT_TX0_P)

JB2-7 (MGT_RX0_N)

JB2-9 (MGT_RX0_P)

JB2-7 to JB2-8

JB2-9 to JB2-10

MGT-lane 1

JB2-14 (MGT_TX1_N)

JB2-16 (MGT_TX1_P)

JB2-13 (MGT_RX1_N)

JB2-15 (MGT_RX1_P)

JB2-13 to JB2-14

JB2-15 to JB2-16

MGT-lane 2

JB2-20 (MGT_TX2_N)

JB2-22 (MGT_TX2_P)

JB2-19 (MGT_RX2_N)

JB2-21 (MGT_RX2_P)

JB2-19 to JB2-20

JB2-21 to JB2-22

MGT-lane 7

JB2-2 (MGT_TX7_P)

JB2-4 (MGT_TX7_N)

JB2-1 (MGT_

RX2

RX7_

N

P)

JB2-

21

3 (MGT_

RX2

RX7_

P

N)

JB2-

19

1 to JB2-

20

2

JB2-

21

3 to JB2-

22

4

MGT-lane
7
4

JB1-3 (MGT_

TX7

TX4_P)

JB1-5 (MGT_

TX7

TX4_N)

JB1-9 (MGT_

RX7

RX4_P)

JB1-11 (MGT_

RX7

RX4_N)

JB1-

3

9 to JB1-

9

3

JB1-

5

11 to JB1-

11

5

MGT-lane
6
5

JB1-15 (MGT_

TX6

TX5_P)

JB1-17 (MGT_

TX6

TX5_N)

JB1-21 (MGT_

RX6

RX5_P)

JB1-23 (MGT_

RX6

RX5_N)

JB1-

15

21 to JB1-

21

15

JB1-

17

23 to JB1-

23

17

Table 4: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.TE0841

Note
Note: The mounted TE 4 x 5 SoMs may have different schematic net-names of the differential signaling pairs of the MGT - lanes. See Schematic of the particular SoM.

...

JTAG access to the mounted SoM is provided through B2B connector JB2 JB3 and is routed to the XMOD header JX1 and also to pin header J3. With the TE0790 XMOD USB2 .0 to JTAG adapter, the FPGA device of the mounted SoM can be programed via USB2 .0 interface.

JTAG Signal

B2B Connector Pin

XMOD Header JX1Pin Header J3Note
TCKJB3-100JX1-4J3-4-
TDIJB3-96JX1-10J3-10-
TDOJB3-98JX1-8J3-8-
TMSJB3-94JX1-12J3-12-

Table 5: JTAG interface signals.

XMOD FTDI JTAG-Adapter Header JX1

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, so in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2 .0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq FPGA device which can be accessed by the USB2 .0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

BOOTMODEE (pin 9)JB1-90JTAGSEL at TE 4 x 5 SoMs standard pin assignment
Pin Schematic NameXMOD Header JX1 PinB2BNote
TCKC (pin 4)JB3-100-
TDOD (pin 8)JB3-98-
TDIF (pin 10)JB3-96-
TMSH (pin 12)JB3-94-
MIO15A (pin 3)JB1-86UART-TX (transmit line)
MIO14B (pin 7)JB1-91UART-RX (receive
line)
line)
RESING (pin 11)JB3-17
System Reset at TE 4 x 5 SoMs standard pin assignment
nRESET signal to the mounted SoM

Table 6: XMOD header JX1 signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4OFF

Table 7: XMOD adapter board DIP-switch positions for voltage configuration.

Note

Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

...

As alternative to the XMOD header JX1, on the Carrier Board carrier board pin header J3 is present, which has a XMOD header-compatible pin-assignment, but also two additional pins (15,16) as differential pairs pair to supply the mounted SoM with an external MGT reference clock signal:

Pin Schematic NameHeader J3 PinB2BNote
TCK4JB3-100-
TDO8JB3-98-
TDI10JB3-96-
TMS12JB3-94-
MIO153JB1-86UART-TX (transmit line)
MIO147JB1-91UART-RX (receive line)
BOOTMODE9
JB1-90usually 'JTAGSEL' on TE 4 x 5 SoMs
RESIN11JB3-17nRESET signal to the mounted SoM
Reset pin
CLK0_N15JB2-32AC decoupled on-board (100 nF capacitor)
CLK0_P16JB2-34AC decoupled on-board (100 nF capacitor)

Table 8: JTAG/UART header J3 signals and connections.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq FPGA device. With the TE0790 XMOD USB2 .0 adapter, the UART signals can be converted to USB2 .0 interface signals:

UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3Note
MIO14JB1-91JX1-7J3-7UART-RX (receive line)
MIO15JB1-86JX1-3J3-3UART-TX (transmit line)

Table 9: UART interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

...

Table 7: SD IO interface signals.

USB2.0 Interface

TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.

Following table gives an overview of the USB2.0 interface signals:

...

JB2-48

...

USB2 Interface

TEBA0841 board has one physical Micro USB2 Type B socket J10, the differential data signals of the USB2 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2 PHY transceiver of the mounted SoM, if available.

With Micro USB2 Type B connector, the USB2 interface is usable in Device or OTG mode.

Following table gives an overview of the USB2 interface signals:

USB2.0 Signal Schematic NameB2BConnected toNote
OTG_N

JB2-48

J10-2USB2 data differential pair
OTG_PJB2-50J10-3
OTG-IDJB2-52J10-4Ground this pin for A-Device (host),  leave floating this pin for B-Device (peripheral).
USB-VBUSJB2-56J10-1USB supply voltage for Host mode. Not supplied by the Carrier Board.

Table 10: USB2 interface signals and connections

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

LED ColorSignal Schematic NameConnected toDescription and Notes
D1GreenMIO9JB1-92available to user
D2RedRLEDJB3-90available to user

Table 11: On-board LEDs

DIP-Switch

There are one 4-bit DIP-witches S1 present on the TEBA0841 board to configure options and set parameters. The following table describes the of the particular switches:

DIP-switch S1Signal Schematic NameConnected toNotes
S1ABOOTMODEJB1-90

The functionalities of all DIP-switches is dependent on the mounted
and used SoM.

The DIP-switch sets control signals, which are usually routed to the
System Controller CPLD of the mounted SoM.

So refer to the Wiki reference page of the SC CPLD firmware of the SoM.

S1BEN1JB1-27
S1CMODEJB1-31
S1DNOSEQJB1-8

Table 12: DIP-switch S1

Table 8: USB2.0 interface signals and connections.

On-board Peripherals

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On-board LEDs

The on-board LEDs are available to the user and can be used to indicate system status and activities:

...

Figure 11: On-board LEDs

VCCIO Selection Jumper

On the TEBA0841 carrier board different VCCIO configurations can be selected by the jumper header J26, J27, J5 and J27J6.

TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on their the B2B connectors, which will be fed with I/O voltage from base-board.

Base-board PL-bank I/O Voltages

Carrier Board B2B PinsStandard Assignment of PL-bank I/O Voltages on TE 4x5 Modules
VCCIOAJB1-10, JB1-12VCCIOA (JM1-9, JM1-11
VCCIOAJB1-10, JB1-12VCCIOA (JM1-9, JM1-11)
VCCIOBJB3-2, JB3-4VCCIOB (JM1-1, JM1-3)
VCCIOCJB3-6VCCIOC (JM1-5)
VCCIOD
JB2
JB3-8,
JB2
JB3-10VCCIOD (JM2-7, JM2-9)

Table 1213: Base-board PL-bank I/O voltages VCCIOA and ... VCCIOD

Note

Note: The corresponding PL-bank I/O voltages of the 4 x 5 SoM to the selectable base-board voltages VCCIOA and ... VCCIOD are depending on the mounted 4 x 5 SoM and varying in order of the used model.

Refer to the SoM's schematic for information about the specific pin assignments on module's B2B-connectors regarding the PL-bank I/O voltages and to the 4 x 5 Module integration Guide for VCCIO voltage options.

Following table describes how to configure the base-board supply-voltages by jumpers:

Base-board PL-bank I/O Voltages
vs Voltage Levels

VCCIOAVCCIOBVCCIOCVCCIOD
1.8VJ26:1-2J5:1-2J6:1-2J27:1-2
2.5VJ26:3-4J5:3-4J6:3-4J27:3-4
3.3V
J26:5-6J5:5-6J6
J26
:5-6J27:5-6

Table 1314: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

Note

Take care of the VCCO voltage ranges of the  particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges.

It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM.

...

The maximum power consumption of the Carrier Board carrier board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
3.3VTBD*

Table 1415: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

...

The external power-supply can be connected to the board by the following pins:

Connector3.3V pinGND pin
JX1

JX1-5, JX1-6,

JX1-1, JX1-2
J3J3-5, J3-6J3-1, J3-2
J4J4-5J4-1, J4-2
J20J20-5, J20-46J20-1 , J20-2 , J20-49 , J20-50
J17J17-5, J17-46J17-1 , J17-2 , J17-49 , J17-50

Table 1516: Connector pins capable for external 3.3V power supply

...

The PL-bank I/O voltages 1.8V, 2.5V and 3.3V will be available after the mounted SoM's 3.3V voltage level has reached stable state on B2B-connector pins JM2-10 and JM2-12 (JB2-9, JB2-11), meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram shows the distribution of the external input voltage of nominal 3.3V to the components:
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TEBA0841-02 power distribution diagram

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Power Rails

The voltage direction of the power rails is from board and on-board connectors' view:

Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

3.3V

Out

2, 4, 6, 14, 16

3.3V module supply voltage
VCCIOAOut10, 12PL IO-bank
VCCIO
VCCO
M1.8VOUTIn401.8V module output voltage
JB2
JB3

3.3V_OUT

In

9, 11

3.3V module output voltage
3.3VOut1, 3, 5, 73.3V module supply voltage
VCCIOBOut2, 4PL IO-bank VCCO
VCCIOCOut6PL IO-bank VCCO
VCCIODOut8, 10PL IO-bank
VCCIO
VCCO
JB3
JB2USB-VBUSOut56USB Host supply voltage

Table 1617: Power pin description of B2B module connector.


PinsNotesJ17
On-board Pin Header DesignatorVCC / VCCIODirection
PinsNotes
J17

3.3V

In / Out

5, 48

3.3V external supply voltage
VCCIODIn / Out6, 45PL IO-bank VCCIO, depends on Jumper settings
J20

3.3V

In / Out

5, 48

3.3V external supply voltage
VCCIOD
VCCIOAIn / Out6, 45PL IO-bank VCCIO, depends on Jumper settings
J20
J43.3V
In /
Out5
, 48
-
3.3V external supply voltageVCCIOAIn / Out6, 45PL IO-bank VCCIO, depends on Jumper settingsJ43.3V
M1.8VOUTOut6-

Table 18: Power Pin description of on-board connector


Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J26VCCIOAIn2, 4, 6-
M1.8VOUTOut1-
2.5VOut3-
3.3V_OUTOut5-
J27

VCCIOD

In2, 4, 6-
M1.8VOUTOut
6
1-

Table 17: Power Pin description of on-board connector.

2.5VOut3-
3.3V_OUTOut5-
J5VCCIOB
Jumper / Header DesignatorVCC / VCCIODirectionPinsNotesJ26VCCIOA
In2, 4, 6-
M1.8VOUTOut1-
2.5VOut3-
3.3V_OUT

Out5-
J27
J6
VCCIOD
VCCIOCIn2, 4, 6-
M1.8VOUTOut1-
2.5VOut3-
3.3V_OUTOut5-
J7VBATIn1-

Table 19Table 18: Power Pin description of VCCIO selection jumper pin header.


Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J10USB-VBUSIn1USB Host supply voltage

Table 1920: Power pin description of peripheral connector.


JTAG Header DesignatorVCC / VCCIODirectionPinsNotes
JX1 (XMOD)3.3VOut5connected to 3.3V external supply voltage
VIO
VCCJTAGOut6
J33.3VOut5connected to 3.3V external supply voltage
3.3VOut6

Table 2021: Power pin description of XMOD/JTAG Connector.connector

Board to Board Connectors

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Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

Vin supply voltage

3.135

3.465

V

3.3V supply-voltage ± 5%,

limitations of the supply voltage depend also
on the technical specifications of the mounted SoM

Storage Temperature

-55105

°C

Molex 74441-0001 Product Specification

Table 2122: Board absolute maximum ratings.

Recommended Operating Conditions

 ParameterMinMaxUnitsNotes
Vin supply voltage3.1353.465V

3.3V supply-voltage ± 5%,

limitations of the supply voltage depend also
on the technical specifications of the mounted SoM

Operating temperature-40+85°CMolex 74441-0001 Product Specification

Table 2223: Module recommended operating conditions.

Operating Temperature Ranges

Industrial TEBA0841 carrier board operating temperature range is industrial grade: -40°C to +85°C.

The TEBA0841 Carrier Board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system .

Physical Dimensions

thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

  • Module size: 56mm × 75mm.  Board size:  PCB 56.47 mm ×  75 mm. Notice that some parts the are hanging slightly over the edge of the PCB like the mini USB-jacks and the SFP+ connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

  • Mating height of the module with standard connectors: 8mm.

  • PCB thickness: ca. 1.65mm.

  • Highest part on the PCB is the SFP+ connector, which has an approximately 11.3 mm 3mm overall hight. Please download the step model for exact numbers.

 The dimensions are given in mm and mil (milli inch).

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Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-02
  • solved Problem with SFP+ connector ('TX FAULT')
  • added VCCIOB and VCCIOC selection jumper
  • new LDO for 2.5V voltage level
  • added DIP-switch for SoM control signals
  • added 2-pin header for VBAT
-TEBA0841-02
-

01

  • First Production Release
PCB patch on SFP+ connector
 
-TEBA0841-01

Table 2324: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Module hardware revision number

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Document Change History

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Date

Revision

Contributors

Description

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  • Update PCB REV02

v.75Ali Naseri, Jan Kumann
  • First TRM release

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