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PS MIO | Function | B2B Pin | Connected to | PS MIO | Function | B2B Pin | Connected to |
---|---|---|---|---|---|---|---|
0 | SPI0 | - | U7-B2, CLK | 40..45 | - | - | Not connected |
1 | SPI0 | - | U7-D2, DO/IO1 | 46 | SD | JM1-17 | B2B, SD_DAT3 |
2 | SPI0 | - | U7-C4, WP/IO2 | 47 | SD | JM1-19 | B2B, SD_DAT2 |
3 | SPI0 | - | U7-D4, HOLD/IO3 | 48 | SD | JM1-21 | B2B, SD_DAT1 |
4 | SPI0 | - | U7-D3, DI/IO0 | 49 | SD | JM1-23 | B2B, SD_DAT0 |
5 | SPI0 | - | U7-C2, CS | 50 | SD | JM1-25 | B2B, SD_CMD |
6 | N/A | - | Not connected | 51 | SD | JM1-27 | B2B, SD_CLK |
7 | SPI1 | - | U17-C2, CS | 52 | USB_PHY | - | U18-31, OTG-DIR |
8 | SPI1 | - | U17-D3, DI/IO0 | 53 | USB_PHY | - | U18-31, OTG-DIR |
9 | SPI1 | - | U17-D2, DO/IO1 | 54 | USB_PHY | - | U18-5, OTG-DATA2 |
10 | SPI1 | - | U17-C4, WP/IO2 | 55 | USB_PHY | - | U18-2, OTG-NXT |
11 | SPI1 | - | U17-D4, HOLD/IO3 | 56 | USB_PHY | - | U18-3, OTG-DATA0 |
12 | SPI1 | - | U17-B2, CLK | 57 | USB_PHY | - | U18-4, OTG-DATA1 |
13..20 | eMMC | - | U6, MMC-D0..D7 | 58 | USB_PHY | - | U18-29, OTG-STP |
21 | eMMC | - | U6, MMC-CMD | 59 | USB_PHY | - | U18-6, OTG-DATA3 |
22 | eMMC | - | U6, MMC-CLKR | 60 | USB_PHY | - | U18-7, OTG-DATA4 |
23 | eMMC | - | U6, MMC-RST | 61 | USB_PHY | - | U18-9, OTG-DATA5 |
24 | ETH | - | U8, ETH-RST | 62 | USB_PHY | - | U18-10, OTG-DATA6 |
25 | USB_PHY | - | U18, OTG-RST | 63 | USB_PHY | - | U18-13, OTG-DATA7 |
26 | MIO | JM1-95 | B2B, as PJTAG MIO possible | 64 | ETH | - | U8-53, ETH-TXCK |
27 | MIO | JM1-93 | B2B, as PJTAG MIO possible | 65..66 | ETH | - | U8-50..51, ETH-TXD0..1 |
28 | MIO | JM1-99 | B2B, as PJTAG MIO possible | 67..68 | ETH | - | U8-54..55, ETH-TXD2..3 |
29 | MIO | JM1-99 | B2B, as PJTAG MIO possible | 69 | ETH | - | U8-56, ETH-TXCTL |
30 | MIO | JM1-92 | B2B (UART RX) | 70 | ETH | - | U8-46, ETH-RXCK |
31 | MIO | JM1-85 | B2B (UART TX) | 71..72 | ETH | - | U8-44..45, ETH-RXD0..1 |
32 | MIO | JM1-91 | B2B | 73..74 | ETH | - | U8-47..48, ETH-RXD2..3 |
33 | MIO | JM1-87 | B2B | 75 | ETH | - | U8-43, ETH-RXCTL |
34..37 | - | - | Not connected | 76 | ETH | - | U8-7, ETH-MDC |
38 | I2C | - | U10-12, SCL | 77 | ETH | - | U8-8, ETH-MDIO |
39 | I2C | - | U10-19, SDA | - | - | - | - |
Table 8: TE0820-02 03 PS MIO mapping
Gigabit Ethernet
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Power Rail Name on B2B Connector | JM1 Pins | JM2 Pins | Direction | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level |
3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board |
1.8V | 39 | - | Output | Internal 1.8V voltage level |
JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" |
VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage |
VCCO_65 | - | 5 | Input | High performance I/O bank voltage |
VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage |
Table 16: TE0820-02 03 power rails
Bank Voltages
Bank | Name on Schematic | Voltage | Range |
---|---|---|---|
64 HP | VCCO_64 | User | HP: 1.0V to 1.8V |
65 HP | VCCO_65 | User | HP: 1.0V to 1.8V |
66 HP | VCCO_66 | User | HP: 1.0V to 1.8V |
500 PSMIO | VCCO_PSIO0_500 | 1.8V | - |
501 PSMIO | VCCO_PSIO1_501 | 3.3V | - |
502 PSMIO | VCCO_PSIO2_502 | 1.8V | - |
503 PSCONFIG | VCCO_PSIO3_503 | 1.8V | - |
504 PSDDR | VCCO_PSDDR_504 | 1.2V | - |
Table 17: TE0820-02 03 I/O bank voltages
See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.
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