Page History

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Date	Vivado	Project Built	Authors	Description
2018-07-12	2018.2	TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip	John Hartfiel	small petalinux changes IO renaming PL Design changes additional notes for FSBL generated with Win SDK changed *.bif
2018-05-17	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip	John Hartfiel	new assembly variant solved Linux flash issue
2018-04-11	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip	John Hartfiel	bugfix TE0803-01-04EG board part file
2018-02-13	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip	John Hartfiel	new assembly variant
2018-02-06	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip	John Hartfiel	same CLK for both VIO
2018-02-05	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip	John Hartfiel	new assembly variant solved JTAG/Linux issue
2018-01-31	2017.4	TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip	John Hartfiel	new assembly variant
2018-01-18	2017.4	TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip	John Hartfiel	initial release

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Software	Version	Note
Vivado	20172018.42	needed
SDK	20172018.42	needed
PetaLinux	20172018.42	needed

Hardware

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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others	Notes
~~TE0803-ES1~~	~~es1_sk~~	REV01	2GB	64MB		Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design
TE0803-01-TE0803-01-02EG-1E	2eg_sk	REV01	2GB	64MB
TE0803-01-02CG-1E	2cg_sk	REV01	2GB	64MB
TE0803-01-03EG-1E	3eg_sk	REV01	2GB	64MB
TE0803-01-03CG-1E	3cg_sk	REV01	2GB	64MB
TE0803-01-02EG-1EA	2eg_sk	REV01	2GB	128MB
TE0803-01-02CG-1EA	2cg_sk	REV01	2GB	128MB
TE0803-01-03EG-1EA	3eg_sk	REV01	2GB	128MB
TE0803-01-03EG-1EB	3egb_sk	REV01	4GB	128MB
TE0803-01-03CG-1EA	3cg_sk	REV01	2GB	128MB
TE0803-01-04CG-1EA	4cg_sk	REV01	2GB	128MB
TE0803-01-04EV-1EA	4ev_sk	REV01	2GB	128MB
TE0803-01-04EV-1E3	4ev_sk	REV01	2GB	128MB	1 mm connectors
TE0803-01-04EG-1EA	4eg_sk	REV01	2GB	128MB
TE0803-01-04CG-1EB	4cg_sk	REV01	2GB	256MB
TE0803-01-05EV-1EA	5ev_sk	REV01	2GB	128MB
TE0803-01-05EV-1IA	5ev_i_sk	REV01	2GB	128MB

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Reference Design is available on:

TE0803 "StarterKit" Reference Design

Design Flow

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Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
Copy image.ub on SD-Card
Insert SD-Card

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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

RGPIO Interface:
- Set Bit 31-28 to "1010" to activat RGPIO Interface of Master or Slave CPLD.Enable to send Write date over RGPIO interface.
  - Important, see description to set correct values
  - Description: TEBF0808 Master CPLD#RGPIO, TEBF0808 Slave CPLD#RGPIO
LED Control +CAN_S:
- - XMOD 2(without green dot) and HD LED are accessible.
Image Added
Image Added

System Design - Vivado

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Block Design

Image RemovedImage Added

PS Interfaces

Activated interfaces:

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Code Block

language	ruby
title	_i_io.xdc


# system controller ip
set#LED_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]HD SC0 J3:31
#LED_XMOD SC17 J3:48 
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S  SC16 J3:46 B26_L1_N

set_property PACKAGE_PIN B13G14 [get_ports BASE_sc11sc0]
set_property PACKAGE_PIN A14D15 [get_ports BASE_sc12sc5]
set_property PACKAGE_PIN B14H13 [get_ports BASE_sc13sc6]
set_property PACKAGE_PIN F13H14 [get_ports BASE_sc14sc7]
set_property PACKAGE_PIN G13A13 [get_ports BASE_sc10_sc15io]
set_property PACKAGE_PIN D15B13 [get_ports BASE_sc5sc11]
set_property PACKAGE_PIN H13A14 [get_ports BASE_sc6sc12]
set_property PACKAGE_PIN H14B14 [get_ports BASE_sc7sc13]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18F13 [get_ports BASE_sc5sc14]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18G13 [get_ports BASE_sc6sc15]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18A15 [get_ports BASE_sc7sc16]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18B15 [get_ports BASE_sc10_iosc17]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18J14 [get_ports BASE_sc11sc18]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18K14 [get_ports BASE_sc12sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15sc6]

# Audio Codec
#LRCLK          J3:49 
#BCLK            J3:51 
#DAC_SDATA    J3:53 
#ADC_SDATA    J3:55 set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property PACKAGE_PINIOSTANDARD L13LVCMOS18 [get_ports LRCLK BASE_sc12]
set_property PACKAGE_PINIOSTANDARD L14LVCMOS18 [get_ports BCLK BASE_sc13]
set_property PACKAGE_PINIOSTANDARD E15LVCMOS18 [get_ports DACBASE_SDATA sc14]
set_property PACKAGE_PINIOSTANDARD F15LVCMOS18 [get_ports ADCBASE_SDATA sc15]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports DACBASE_SDATA sc18]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
#LED
#LED_HD SC0 J3:31 BASE_sc19]

# Audio Codec
#LRCLK          J3:49 
#BCLK            J3:51 
#DAC_SDATA    J3:53 
#ADC_SDATA    J3:55 
set_property PACKAGE_PIN G14L13 [get_ports {LED_HD[0]} LRCLK ]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18L14 [get_ports {LED_HD[0]}]
#LED_XMOD SC17 J3:48  BCLK ]
set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN B15F15 [get_ports {LED_XMOD2[0]}ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports {LED_XMOD2[0]}]

# CAN
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S  SC16 J3:46 B26_L1_N

set_property PACKAGE_PIN A15 [get_ports CAN_0_S LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports CANADC_0_S ]
set_property PACKAGE_PIN K14 [get_ports CAN_0_rx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_rx ]
set_property PACKAGE_PIN J14 [get_ports CAN_0_tx ]
set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ]

Software Design - SDK/HSI

SDATA ]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 20172018.4 2 FSBL

Changes:

Si5338ConfigurationSi5345Configuration, PCIe Reset over GPIO see
- see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
- Add
register_map
- Si5345-Registers.h,
si5338
- si5345.c,
si5338
- si5345.h

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_fsbl_flash

TE modified 20172018.4 2 FSBL

Changes:

Set FSBL Boot Mode to JTAG
Disable Memory initialisation

PMU

Xilinx default PMU firmware.

Hello TE0803

Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0803

Hello TE0808 Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

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u-

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boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

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PetaLinux KICKstart

Config

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Activate:
SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT

U-Boot

Change platform-top.h

Code Block

language	js

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
_BOOTM_LEN 0xF000000
 
#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
 
#define DFU_ALT_INFO_RAMMMC \
                "dfu_rammmc_info=" \
        "setenvset dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0${kernel_image} fat 0 1\\\\;" \
        "dfu_rammmc=run dfu_rammmc_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 rammmc 0\0"

#define DFU_ALT_INFO " \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc   DFU_ALT_INFO_RAM
0\0"
 
/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
 
/*select sd instead of mmc for autoboot */

#define CONFIG_BOOTCOMMAND    "run uenvboot;  mmcinfo && fatload mmc 1 ${netstart} ${kernel_img};bootm ${netstart}"


Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0x20
#endif

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};

/* default */

/* SD */

&sdhci1 {
    // disable-wp;
    no-1-8-v;

};

/* USB  */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
};

/* ETH PHY */

&gem3 {
    phy-handle = <&phy0>;
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;

        i2c@2 { // PCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // i2c SFP
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // i2c SFP
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // i2c EEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // i2c FMC
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;

            si570_2: clock-generator3@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <78800000>;
            };
        };
        i2c@7 { // i2c USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // i2c PMOD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
            /*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
            */
        };
        i2c@2 { // i2c FireFly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // i2c FireFly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { // i2c PLL
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // i2c SC
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { // i2c
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // i2c
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
};

/* UNUSED DMA disable */

&lpd_dma_chan1 {
    status = "disabled";
};
&lpd_dma_chan2 {
    status = "disabled";
};
&lpd_dma_chan3 {
    status = "disabled";
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

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See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

adau1761init

Audio initialisation.

Additional Software

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Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

	modified-user
	modified-user

Release 2018.2

17 May 2018

v.14

John Hartfiel

new assembly variant
solved known issues

30 Apr 2018

v.13

John Hartfiel

Update known Issues

11 Apr 2018

v.12

John Hartfiel

bugfix board part files

13 Feb 2018

v.11

John Hartfiel

new assembly variant
solved known issues

2018-01-29

v.4

John Hartfiel

Update known Issues

2018-01-18

v.3

John Hartfiel

Release 2017.4

All

Page info

	modified-users
	modified-users

...

Trenz Electronic Documentation

Versions Compared

Old Version 14

New Version 15

Key

Hardware

Design Flow

System Design - Vivado

Block Design

PS Interfaces

Software Design - SDK/HSI

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

PMU

Hello TE0803

zynqmp_pmufw

hello_te0803

u-

boot

Config

Activate:
SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT

U-Boot

Device Tree

adau1761init

Additional Software

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 14

New Version 15

Key

Hardware

Design Flow

System Design - Vivado

Block Design

PS Interfaces

Software Design - SDK/HSI

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

PMU

Hello TE0803

zynqmp_pmufw

hello_te0803

u-

boot

Config

Activate:SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT

U-Boot

Device Tree

adau1761init

Additional Software

Activate:
SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT