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Refer to https://wiki.trenz-electronic.de/display/PD/TE0715+TRM for online version of this manual and the rest of available documentation. |
The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GByte of DDR3 SDRAM, 32MBytes of SPI Flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.
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Table 4: MGT lanes overview.
Below are listed MGT bank reference clock sources.
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Table 6: JTAG interface signals.
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JTAGEN pin in B2B connector JM1 should be kept low or grounded for normal operation. |
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Source | Signal | Frequency | Destination | Pin Name | Notes | |
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U18 | CLK | 25.000000 MHz | U10 | IN3 | ||
U9 | CLK | 25.000000 MHz | U7 | XTAL_IN | ||
U11 | PS-CLK | 33.333333 MHz | U5 | PS_CLK_500 | Zynq SoC PS subsystem main clock. | |
U15 | CLK | 52.000000 MHz | U6 | REFCLK | USB3320C PHY reference clock. |
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Figure 4: TE0820-02 power-on sequence diagram.
For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up
Warning |
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out (3.3V (JM2-10, 12) or 1.8V(JM1-39) output) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
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B2B Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Note | |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. | |
3.3VIN | 13, 15 | - | Input | Supply voltage. | |
VCCIO13 | 9, 11 | - | Input | High range bank voltage. | |
VCCIO34 | - | 5 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. | |
VCCIO35 | - | 7, 9 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. | |
VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. | |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. | |
1.8V | 39 | - | Output | Internal 1.8V voltage level. | |
DDR_PWR | - | 19 | Output | Internal 1.5V or 1.35V voltage level, depends on revision. | |
VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
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Variants Currently in Production
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Temperature
Range
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B2B Connector
Height
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Trenz shop TE0715 overview page | |
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English page | German page |
Table 18: TE0715 variants Table 18: TE0715 variants currently in production.
Technical Specifications
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Table 19: TE0715 module absolute maximum ratings.
Note |
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Assembly variants for higher storage temperature range are available on request. |
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Parameter | Min | Max | Units | Notes | Reference Document | ||
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VIN supply voltage | 2.5 | 5.5 | V | ||||
3.3VIN supply voltage | 3.135 | 3.465 | V | ||||
VBAT_IN supply voltage | 2.7 | 5.5 | V | ||||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |||
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 | ||
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 | ||
I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 | ||
Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Table 20: TE0715 module recommended operating conditions.
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Date | Revision | Notes | Link to PCN | Documentation Link | ||
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2016-06-21 | 04 | Second production release | Click to see PCN | TE0715-04 | ||
- | 03 | First production release | TE0715-03 | |||
- | 02 | Prototypes | TE0715-02 | |||
- | 01 | Prototypes | Prototypes |
Table 21: TE0715 module hardware revision history.
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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v.85 | John Hartfiel |
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2017-09-10 | v.82 | Jan Kumann |
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2017-06-07 | v.64 | Jan Kumann |
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2017-03-02 | v.59 | Thorsten Trenz |
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2017-02-10 | v.58 | Thorsten Trenz |
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2017-01-25 | v.55
| Jan Kumann |
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2017-01-14 | v.50 | Jan Kumann |
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2016-11-15 | v.45 | Thorsten Trenz |
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2016-10-18 | v.40 | Ali Naseri |
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2016-06-28 | v.38 | Thorsten Trenz, Emmanuel Vassilakis, Jan Kumann |
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2016-04-27 | v.33 | Thorsten Trenz, Emmanuel Vassilakis |
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2016-03-31 | v.10 | Philipp Bernhardt, Antti Lukats |
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