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Pin Name | SC CPLD Direction | Function | Default Configuration |
---|---|---|---|
200MHZCLK_EN | out | control line | enables 200.0000MHz oscillator U1 |
BUTTON | in | user | Reset Button |
CPLD_TDO | out | CPLD JTAG interface | - |
CPLD_TDI | in | ||
CPLD_TCK | in | ||
CPLD_TMS | in | ||
JTAG_EN | in | ||
DDR3_SCL | in / out | I²C bus of DDR3 SODIMM socket | I²C connected to FPGA |
DDR3_SDA | in / out | ||
PLL_SCL | in / out | I²C bus of SI5338 quad clock PLL | I²C connected to FPGA |
PLL_SDA | in / out | ||
PCIE_RSTB | in | PCIe reset input | see current SC CPLD firmware |
FEX_DIR / FEX0 ... FEX11 | in / out | user GPIO | see current SC CPLD firmware |
F1PWM | out | FPGA FAN control | see current SC CPLD firmware |
F1SENSE | in | ||
FAN_FMC_EN | out | FMC FAN enable | |
FMC_PG_C2M | out | FMC signals and pins | see current SC CPLD firmware |
FMC_PG_M2C | in | ||
FMC_PRSNT_M2C_L | in | ||
FMC_SCL | in / out | FMC I²C | I²C connected to FPGA |
FMC_SDA | in / out | ||
FMC_TCK | FMC JTAG | see current SC CPLD firmware | |
FMC_TDI | |||
FMC_TDO | |||
FMC_TMS | |||
FMC_TRST | |||
DONE | in | FPGA configuration signal | PL configuration completed |
PROGRAM_B | out | PL configuration reset signal | |
LED1 | out | LED status signal | see current CPLD firmware |
FPGA_IIC_OE | in | SC CPLD works as I²C switch with the FPGA as I²C-Master and on-board peripherals as I²C-slaves | I²C output enable, connected to PL bank 14 pin F25 |
FPGA_IIC_SCL | in / out | I²C clock line, connected to PL bank 14 pin G26 | |
FPGA_IIC_SDA | in / out | I²C data line, connected to PL bank 14 pin G25 | |
EN_1V8 | out | Power control | enable signal DCDC U20 '1V8' |
PG_1V8 | in | power good signal DCDC U20 '1V8' | |
EN_3V3FMC | out | enable signal DCDC U15 'EN_3V3FMC' | |
PG_3V3 | in | power good signal U15 'EN_3V3FMC' | |
EN_FMC_VADJ | out | enable signal DCDC U7 'FMC_VADJ' | |
PG_FMC_VADJ | in | power good DCDC U7 'FMC_VADJ' | |
VID0_FMC_VADJ, | out | DCDC U7 power selection pin | |
VID0_FMC_VADJ_CTRL, | in | Power selection of FMC_VADJ, forwarded to DCDC U7 | |
LTM_1V5_RUN | out | enable signals of DCDC U3, U4 (LTM4676) see current CPLD firmware | |
LTM_4V_RUN | out | ||
LTM_SCL | in / out | DCDC U3, U4 (LTM4676) I²C | I²C connected to FPGAAddress U3: 0x40 I²C Address U4: 0x4F I²C interface of LTM4676 ICs |
LTM_SDA | in / out | ||
LTM1_ALERT | in | DCDC U3, U4 (LTM4676) control, active low | see current CPLD firmware |
LTM2_ALERT | in | ||
LTM_1V_IO0 | in / out | ||
LTM_1V_IO1 | in / out | ||
LTM_1V5_4V_IO0 | in / out | ||
LTM_1V5_4V_IO1 | in / out |
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DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes |
---|---|---|---|---|
S1-1 | JTAG_EN | SC CPLD U5, bank 1, pin 82 | enables JTAG interface of SC CPLD U5 | SC CPLD programmable through JTAG connector, J8 |
S1-2 | VID0_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 71 | set 3bit code to adjust FMC_VADJ voltage | The FMC_VADJ voltage is provided by DCDC U7 EN5365QI, the voltage can be adjusted from 0.8V to 3.3V in 7 steps: Set DIP-switches as bit pattern "S1-4 | S1-3 | S1-2: FMC_VADJ": 0 | 0 | 0 : 3.3V |
S1-3 | VID1_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 63 | ||
S1-4 | VID2_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 62 |
Table 17: DIP-switch S1 functionality description
DC-DC Converters
On-board DC-DC converters U3 (1V5 and 4V) and U4 (1V) are provided by Linear Technology LTM4676 with special I/O's and I²C interface:
...
'LTM_SDA'
'LTM_SCL'
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SC CPLD U5, pin 66
SC CPLD U5, pin 67
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I²C Address: 0x40
I²C interface of LTM4676
also accessible through header J10
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SDA, pin D6
SCL, pin E6
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'LTM_SDA'
'LTM_SCL'
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SC CPLD U5, pin 66
SC CPLD U5, pin 67
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I²C Address: 0x4F
I²C interface of LTM4676
also accessible through header J10
...
8V | ||
S1-3 | VID1_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 63 |
S1-4 | VID2_FMC_VADJ_CTRL | SC CPLD U5, bank 1, pin 62 |
Table 17: DIP-switch S1 functionality descriptionTable 18: DCDC converters U3 and U4 I/O's and interfaces
Power and Power-On Sequence
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Power Input | Typical Current |
---|---|
12V VIN | TBD* |
Table 1918: Typical power consumption
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Bank | Schematic Name | Voltage | Range | Notes |
---|---|---|---|---|
0 | 1V8 | 1.8V | - | Config bank 0 fixed to 1.8V |
12 | FMC_VADJ | user | HR: 1.2V to 3.3V | FMC_VADJ voltage ajustable by DIP switch S1 |
13 | FMC_VADJ | user | HR: 1.2V to 3.3V | FMC_VADJ voltage ajustable by DIP switch S1 |
14 | 1V8 | 1.8V | HR: 1.2V to 3.3V | PL bank 14 fixed to 1.8V |
15 | FMC_VADJ | user | HR: 1.2V to 3.3V | FMC_VADJ voltage ajustable by DIP switch S1 |
16 | VIO_B_FMC | user | HR: 1.2V to 3.3V | PL bank 16 fixed to 1.8V |
32 | 1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
33 | 1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
34 | 1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
115 116 | MGTAVCC_FPGA MGTVCCAUX_FPGA MGTAVTT_FPGA | 1.0V 1.8V 1.2V | MGT bank supply voltage MGT bank auxiliary supply voltage MGT bank termination circuits voltage | MGT banks with Xilinx GTX transceiver units |
Table 2019: Board I/O bank voltages
Power Rails
Connector / Pin | Voltage | Direction | Notes |
---|---|---|---|
J4, pin 2 | 12V | Output | 4-wire PWM fan connector supply voltage |
J6, pin 2 | 5V | Output | Cooling fan M1 supply voltage |
J8, pin 6 | 3V3 | Output | VCCIO CPLD JTAG |
J9, pin 2 | 1V8 | Output | VCCIO FPGA JTAG |
J2, pin C35 / C37 | 12V | Output | FMC supply voltage |
J2, pin D32 | 3V3 | Output | VCCIO FMC |
J2, pin D36 / D38 / D39 / D40 | 3V3FMC | Output | VCCIO FMC |
J2, pin H1 | VREF_A_M2C | Input | VREF voltage for bank 13 / 15 |
J2, pin K1 | VREF_B_M2C | Input | VREF voltage for bank 16 |
J2, pin J39 / J40 | VIO_B_FMC | Input | PL I/O voltage bank 16 (VCCO) |
J2, pin H40 / G39 / F40 / E39 | FMC_VADJ | Output | PL I/O voltage bank 12 / 13 / 15 (VCCO) |
J1, pin B1 / B2 / B3 / A2 / A3 | 12V_input_B | Input | 12V main power supply from PCIe connector |
J5, pin 1 / 2 / 3 | 12V_input_A | Input | Main power supply connector |
Table 2120: Board power rails
Variants Currently In Production
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Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | -0.3 | 20 | V | TPS6217 datasheet Note: voltage limitations are not valid for connected FMC module and/or FPGA FAN |
Supply voltage for HR I/O banks (VCCO) | -0.500 | 3.600 | V | Xilinx datasheet DS182 |
Supply voltage for HP I/O banks (VCCO) | -0.500 | 2.000 | V | Xilinx datasheet DS182 |
I/O input voltage for HR I/O banks | -0.500 | VCCO + 0.500 | V | Xilinx datasheet DS182 |
I/O input voltage for HP I/O banks | -0.500 | VCCO + 0.500 | V | Xilinx datasheet DS182 |
Reference Voltage pin (VREF) | -0.500 | 2 | V | Xilinx datasheet DS182 |
Differential input voltage | -0.5 | 2.625 | V | Xilinx datasheet DS182 |
I/O input voltage for SC CPLD U5 | -0.5 | 3.75 | V | Lattice MachXO2 Family datasheet |
GTX transceiver reference clocks absolute input voltage | -0.500 | 1.320 | V | Xilinx datasheet DS182 |
GTX transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.500 | 1.260 | V | Xilinx datasheet DS182 |
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10 | -0.3 | 5.5 | V | LTM4676A datasheet |
Storage temperature | -40 | +100 | °C | SML-P11 LED datasheet |
Table 2221: Module absolute maximum ratings
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Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 11.4 | 12.6 | V | 12V nominal, ANSI/VITA 57.1 power specification for FMC connector |
Supply voltage for HR I/O banks (VCCO) | 1.140 | 3.465 | V | Xilinx datasheet DS182 |
Supply voltage for HP I/O banks (VCCO) | 1.140 | 1.890 | V | Xilinx datasheet DS182 |
I/O input voltage for HR I/O banks | -0.500 | VCCO + 0.20 | V | Xilinx datasheet DS182 |
I/O input voltage for HP I/O banks | -0.500 | VCCO + 0.20 | V | Xilinx datasheet DS182 |
Differential input voltage | -0.2 | 2.625 | V | Xilinx datasheet DS182 |
I/O input voltage for SC CPLD U5 | -0.3 | 3.6 | V | Lattice MachXO2 Family datasheet |
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10 | 0 | 3.3V | V | LTM4676A datasheet |
Board Operating Temperature Range 1), 2) | -40 | 85 | °C | board operating temperature range limited by FPGA SoC and on-board peripherals |
Table 2322: Module recommended operating conditions
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Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 02 | current available board revision | - | - |
- | 01 | First production release | PCN-20180524 TEF1001-01 | TEF1001-01 |
Table 2423: Module hardware revision history
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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Table 2524: Document change history
Disclaimer
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