Page History
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Date | Vivado | Project Built | Authors | Description |
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2018.09.04 | 2018.2 | TE0807-StarterKit_noprebuilt-vivado_2018.2-build_03_20180904122245.zip TE0807-StarterKit-vivado_2018.2-build_03_20180904121600.zip | John Hartfiel |
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2018.05.24 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip | John Hartfiel |
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2018-02-06 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip | John Hartfiel |
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2018-02-05 | 2017.4 | TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip | John Hartfiel |
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2018-01-18 | 2017.4 | TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip | John Hartfiel |
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Software | Version | Note |
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Vivado | 20172018.42 | needed |
SDK | 20172018.42 | needed |
PetaLinux | 20172018.42 | needed |
Hardware
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<!-- Hardware Support --> |
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Reference Design is available on:
Design Flow
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<!-- Basic Design Steps Add/ Remove project specific --> |
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- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Optional "TE::pr_program_flash_binfile -swapp hello_te0807" possible - Copy image.Copy image.ub on SD-Card
- Insert SD-Card
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<!-- Description of Block Design, Constrains... BD Pictures from Export... --> |
Block Design
PS Interfaces
Activated interfaces:
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#LED_HD SC0 J3:31 #System Controller IP #J3:31 LED_HD set_property PACKAGE_PIN K11 [get_ports {LED_HD[0]}]BASE_sc0] #J3:41 set_property IOSTANDARDPACKAGE_PIN LVCMOS18E14 [get_ports {LED_HD[0]}] #LED_XMOD SC17 J3:48 BASE_sc5] #J3:45 set_property PACKAGE_PIN B12C12 [get_ports {LED_XMOD2[0]}]BASE_sc6] #J3:47 set_property IOSTANDARDPACKAGE_PIN LVCMOS18D12 [get_ports {LED_XMOD2[0]}] #System Controller IPBASE_sc7] #J3:32 set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io] #J3:34 set_property PACKAGE_PIN K13 [get_ports BASE_sc11] #J3:36 set_property PACKAGE_PIN A13 [get_ports BASE_sc12] #J3:38 set_property PACKAGE_PIN A14 [get_ports BASE_sc13] #J3:40 set_property PACKAGE_PIN E12 [get_ports BASE_sc14] #J3:42 set_property PACKAGE_PIN F12 [get_ports BASE_sc15] #J3:4146 CAN S set_property PACKAGE_PIN E14A12 [get_ports BASE_sc5sc16] #J3:4548 LED_XMOD set_property PACKAGE_PIN C12B12 [get_ports BASE_sc6sc17] #J3:4750 CAN TX set_property PACKAGE_PIN D12B14 [get_ports BASE_sc7]sc18] #J3:52 CAN RX set_property IOSTANDARDPACKAGE_PIN LVCMOS18C14 [get_ports BASE_sc5sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_iosc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_sc12io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15sc13] # PLL #J4:74 #set_property PACKAGE_PIN AF15set_property IOSTANDARD LVCMOS18 [get_ports {si570_clk_p[0]}] #setBASE_sc14] set_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_p[0]}BASE_sc15] #setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_n[0]}] # Audio Codec #LRCLK J3:49 B47_L9_N BASE_sc16] set_property PACKAGE_PINIOSTANDARD G14LVCMOS18 [get_ports LRCLK ] #BCLK J3:51 B47_L9_PBASE_sc17] set_property PACKAGE_PINIOSTANDARD H14LVCMOS18 [get_ports BCLK ] #DAC_SDATA J3:53 B47_L7_NBASE_sc18] set_property PACKAGE_PINIOSTANDARD C13LVCMOS18 [get_ports DACBASE_SDATA sc19] #ADC_SDATA J3:55 B47_L7_P set# PLL #J4:74 #set_property PACKAGE_PIN D14AF15 [get_ports ADC_SDATA ] set{si570_clk_p[0]}] #set_property IOSTANDARD LVCMOS18LVDS [get_ports LRCLK ] set_property IOSTANDARD LVCMOS18 [get_ports BCLK ] set{si570_clk_p[0]}] #set_property IOSTANDARD LVCMOS18LVDS [get_ports DAC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ] # CAN #CAN RX SC19 J3:52 B47_L10_P #CAN TX SC18 J3:50 B47_L10_N #CAN S SC16 J3:46 B47_L12_N {si570_clk_n[0]}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN A12G14 [get_ports CAN_0_SLRCLK ] set_property IOSTANDARDPACKAGE_PIN LVCMOS18H14 [get_ports CAN_0_SBCLK ] set_property PACKAGE_PIN C14C13 [get_ports CANDAC_0_rxSDATA ] set_property IOSTANDARDPACKAGE_PIN LVCMOS18D14 [get_ports CANADC_0_rxSDATA ] set_property PACKAGE_PINIOSTANDARD B14LVCMOS18 [get_ports CAN_0_txLRCLK ] set_property IOSTANDARD LVCMOS18 [get_ports CAN_0_tx ]BCLK ] set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ] |
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
SDK template in ./sw_lib/sw_apps/ available.
FSBL
TE modified 20172018.4 2 FSBL
Changes:
- Si5345Configuration, PCIe Reset over GPIO see
- See xfsbl_board.c and xfsbl_board.h
- Add Si5345-Registers.h, si5345.c, si5345.h
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
zynqmp_fsbl_flash
TE modified 20172018.4 2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
PMU
Xilinx default PMU firmware.
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hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
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u-
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noot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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Config
No changes.
U-Boot
- Change platform-top.h
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#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define CONFIG_SYS_BOOTM_LEN 0xF000000 DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_RAMMMC \ "dfu_rammmc_info=" \ "setenvset dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0${kernel_image} fat 0 1\\\\;" \ "dfu_rammmc=run dfu_rammmc_info && dfu 0 rammmc 0\0" \ "thor_rammmc=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO \ DFU_ALT_INFO_RAM mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*select sd instead of mmc for autobootDefine CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */ #define CONFIG_BOOTCOMMAND#ifdef CONFIG_ZYNQMP_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_CMD_EEPROM #define CONFIG_ZYNQ_EEPROM_BUS "run uenvboot; mmcinfo && fatload mmc 1 ${netstart} ${kernel_img};bootm ${netstart}" 5 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 #endif |
Device Tree
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/include/ "system-conf.dtsi" / { }; /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c SFP #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_2: clock-generator3@5d { #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <78800000>; }; }; i2c@7 { // i2c USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // i2c PMOD #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // i2c FireFly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2c FireFly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // i2c PLL #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // i2c SC #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // i2c #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* UNUSED DMA disable */ &lpd_dma_chan1 { status = "disabled"; }; &lpd_dma_chan2 { status = "disabled"; }; &lpd_dma_chan3 { status = "disabled"; }; &lpd_dma_chan4 { status = "disabled"; }; &lpd_dma_chan5 { status = "disabled"; }; &lpd_dma_chan6 { status = "disabled"; }; &lpd_dma_chan7 { status = "disabled"; }; &lpd_dma_chan8 { status = "disabled"; }; |
Kernel
Deactivate:
CONFIG_CPU_IDLE (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ (only needed to fix JTAG Debug issue)
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v.12 | John Hartfiel |
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v.10 | John Hartfiel |
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v.9 | John Hartfiel |
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2018-01-29 | v.4 | John Hartfiel |
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2018-01-18 | v.3 | John Hartfiel |
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