Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

  • Zynq UltraScale+ MPSoC ZU15

  • Front side interface connectors
    • RJ-45 GbE Ethernet interface
    • Elbow Socket with 4x on-board 8bit DAC output
    • MicroSD Card connector
    • USB2 and USB3 to FIFO bridge connector
    • 4x status LEDs
  • 4 CompactPCI slots for backplane connection (3U form factor)
    • 24 GTH lanes
    • 4 PS GTR lanes
    • USB2 interface
    • 64 Zynq PL HP I/O's
    • 8x PLL clock input
    • JTAG, I²C and 7 user I/O's to MAX10 FPGA
  • 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

  • Dual parallel QSPI Flash (bootable), 512 MByte maximum

  • 26-pin header with 20 Zynq PL HD I/O's
  • 3-pin header with 2 MAX10 FPGA I/O's
  • System Controller (Altera MAX10 FPGA SoC)
    • Power Sequencing
    • System management and control for MPSoC and on-board peripherals
  • Si5345 programmable 10 output PLL clock generator
  • Si53340 Quad and Dual PLL clock generatorsgenerator
  • 2x 4bit DIP switches
  • 1x user push button
  • Zynq MPSoC cooling FAN connector
  • On-board high-efficiency DC-DC converters

...

Scroll Title
anchorFigure_1
titleFigure 1: TEC0850-02 block diagram
Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision12
diagramNameTEC0850 overview
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641

Scroll Only

...

  1. GbE RJ-45 MagJack, J7
  2. DAC output 5-pin elbow receptacle socket, J15
  3. Micro USB2 B receptacle connector, J9
  4. MicroSD Card socket, J11
  5. USB C connector, J10
  6. LED light pipes J14 integrating LEDs D1 ... D4
  7. 4bit DIP-switch, S2
  8. 4bit DIP-switch, S1
  9. FTDI FT2232 USB2 to FIFO bridge, U4
  10. 3-pin header, J8
  11. MAX10 FPGA JTAG/UART 10-pin header, J13
  12. Altera MAX10 FPGA System Controller FPGA, U18
  13. 4-Wire PWM fan connector, J17
  14. Zynq MPSoC PL I/O 26-pin header, J16
  15. DDR4 SO-DIMM 260-pin socket, U3
  16. Battery Holder CR1220, B1
  17. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
  18. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
  19. DC-DC Converter LT8471IFE @+5VA/-5VA, U74
  20. DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
  21. DC-DC Converter 171050601 @5V, U50
  22. Xilinx Zynq Ultrascale+ MPSoC, U1
  23. Si5345A 10-output I²C programmable PLL clock, U14
  24. Main power fuse @2.5A/16V, F1
  25. cPCI slot, J1
  26. cPCI slot, J4
  27. cPCI slot, J5
  28. cPCI slot, J6
  29. FTDI FT601Q USB3 to FIFO bridge, U9
  30. TI THS5641 8bit DAC ,U28
  31. TI THS5641 8bit DAC ,U31
  32. TI THS5641 8bit DAC ,U29
  33. TI THS5641 8bit DAC ,U33
  34. Marvell Alaska 88E1512 GbE PHY ,U20

...

Scroll Title
anchorFigure_4
titleFigure 4: Power-On Sequence Diagram
Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision2
diagramNameTEC0850 Power-On Sequence Diagram
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641

Scroll Only

Voltage Monitor Circuit

Scroll Title
anchorFigure_4
titleFigure 4: Power-On Sequence Diagram
Scroll Ignore

draw.io Diagram
bordertrue
viewerToolbartrue
fitWindowfalse
diagramNameTEC0850 Voltage Monitor Circuit

Power Rails

...

simpleViewerfalse
width
diagramWidth642
revision1

Scroll Only


Power Rails

Scroll Title
anchorTable_x
titleTable x: Module absolute maximum ratings.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Connector / PinVoltageDirectionNotes
J1, pin A1, D1, E1, G1, H1, J1, K1VIN_12VInputMain power supply pins
J17, pin 212VOutput4-wire PWM fan connector supply voltage
J13, pin 4+3V_DOutputJTAG/UART reference VCCIO voltage
B1, pin +VBATTInput3.0V CR1220 battery
J16, pin 25VOutputI/O header VCCIO
J16, pin 13.3VOutputI/O header VCCIO
J9, pin 4VBUSInputUSB2 VBUS (5.0V nominal)
J10, pin A4, B9VBUS30InputUSB3 VBUS (5.0V nominal)
J11, pin 43.3VOutputMicroSD Card VDD
J15, pin 2DAC1_OUTOutputDAC output
J15, pin 3DAC2_OUTOutputDAC output
J15, pin 4DAC3_OUTOutputDAC output
J15, pin 5DAC4_OUTOutputDAC output

Bank Voltages

Scroll Title
anchorTable_x
titleTable x: Module absolute maximum ratings.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Zynq MPSoC BankTypeSchematic NameVoltageVoltage Range
44HD3.3V3.3Vfixed to 3.3V
47HD3.3V3.3Vfixed to 3.3V
48HD3.3V3.3Vfixed to 3.3V
49HD3.3V3.3Vfixed to 3.3V
50HD3.3V3.3Vfixed to 3.3V
64HPPL_1V81.8Vfixed to 1.8V
65HPPL_1V81.8Vfixed to 1.8V
66HPPL_1V81.8Vfixed to 1.8V
67HPPL_1V81.8Vfixed to 1.8V
500MIOPS_1V81.8Vfixed to 1.8V
501MIOPS_1V81.8Vfixed to 1.8V
502MIOPS_1V81.8Vfixed to 1.8V
503CONFIGPS_1V81.8Vfixed to 1.8V
504PSDDRDDR_1V2
DDR_PLL

1.2V
1.8V

fixed bank voltages

128

129

130

GTH

AVCC_L

AUX_L

AVTT_L

0.9V

1.8V

1.2V

fixed bank voltages

228

229

230

GTH

AVCC_R

AUX_R

AVTT_R

0.9V

1.8V

1.2V

fixed bank voltages
MAX10 FPGA BankTypeSchematic NameVoltageVoltage Range
1A-+3V_D3.3Vfixed to 3.3V
1B-+3V_D3.3Vfixed to 3.3V
2-PS_1V81.8Vfixed to 1.8V
3-3.3V3.3Vfixed to 3.3V
5-+3V_D3.3Vfixed to 3.3V
6-+3V_D3.3Vfixed to 3.3V
8-+3V_D3.3Vfixed to 3.3V

Technical Specifications

Absolute Maximum Ratings

...