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The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide data bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • Zynq UltraScale+ MPSoC ZU15

  • Front side interface connectors
    • RJ-45 GbE Ethernet interface
    • Circular push/pull connector with 4x on-board 8bit DAC output
    • MicroSD Card connector
    • USB 2.0 and USB 3.0 to FIFO bridge connector
    • 4x status LEDs
  • 4 CompactPCI Serial connectors for backplane connection (3U form factor)
    • 24 GTH lanes
    • 4 PS GTR lanes
    • USB 2.0 interface
    • 64 Zynq PL HP I/O's
    • 8x PLL clock input
    • JTAG, I²C and 7 user I/O's to MAX10 FPGA
  • 64bit DDR4 SODIMM (PS connected), 8 GByte maximum

  • Dual parallel QSPI Flash (bootable), 512 MByte maximum

  • 26-pin header with 20 Zynq PL HD I/O's
  • 3-pin header with 2 MAX10 FPGA I/O's
  • System Controller (Altera MAX10 FPGA SoC)
    • Power Sequencing
    • System management and control for MPSoC and onboard peripherals
  • Si5345 programmable 10 output PLL clock generator
  • Si53340 Quad clock buffer
  • 2x 4bit DIP switches
  • 1x user push button
  • Zynq MPSoC cooling FAN connector
  • On-board high-efficiency DC-DC converters

Block Diagram

TEC0850-02 block diagram

Main Components

TEC0850-02 main components

  1. GbE RJ-45 MagJack, J7
  2. 5-pin circular push/pull receptacle connector for DAC output, J15
  3. Micro USB 2.0 B receptacle connector, J9
  4. MicroSD Card socket, J11
  5. USB 3.0 Type C connector, J10
  6. LED light pipes J14 integrating LEDs D1 ... D4
  7. 4bit DIP-switch, S2
  8. 4bit DIP-switch, S1
  9. FTDI FT2232 USB 2.0 to UART/JTAG bridge, U4
  10. 3-pin PicoBlade header, J8
  11. MAX10 FPGA JTAG/UART 10-pin header, J13
  12. Altera MAX10 System Controller FPGA, U18
  13. 4-Wire PWM fan connector, J17
  14. 26-pin IDC header for FPGA PL I/O's, J16
  15. DDR4 SO-DIMM 260-pin socket, U3
  16. Battery Holder CR1220, B1
  17. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
  18. 256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
  19. DC-DC Converter LT8471IFE @+5VA/-5VA, U74
  20. DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
  21. DC-DC Converter 171050601 @5V, U50
  22. Xilinx Zynq Ultrascale+ MPSoC, U1
  23. Si5345A 10-output I²C programmable PLL clock, U14
  24. Main power fuse @2.5A/16V, F1
  25. cPCI connector, J1
  26. cPCI connector, J4
  27. cPCI connector, J5
  28. cPCI connector, J6
  29. FTDI FT601Q USB 3.0 to FIFO bridge, U9
  30. TI THS5641 8bit DAC ,U28
  31. TI THS5641 8bit DAC ,U31
  32. TI THS5641 8bit DAC ,U29
  33. TI THS5641 8bit DAC ,U33
  34. Marvell Alaska 88E1512 GbE PHY ,U20

Initial Delivery State

Storage device name



User configuration EEPROMs (1x Microchip 24AA128T-I/ST, 1x Microchip 24AA025E48T-I/OT)EmptyNot programmed
USB 2.0 to UART/JTAG bridge configuration EEPROM (ST M93C66)EmptyNot programmed
Si5345A programmable PLL NVM OTPEmptyNot programmed
2x QSPI Flash memoryEmptyNot programmed
Initial delivery state of programmable devices on the module

Control Signals

To get started with TEC0850 board, some initial signals should be set described in the following table:

Control signal

Switch / ButtonSignal Schematic Names

Connected to


SC JTAGENS1-1JTAGENSC FPGA U18, bank 1B, pin E5OFF: MAX 10 JTAG enabled,
ON: Zynq MPSoC JTAG enabled
EEPROM WPS1-2WPEEPROM U63, pin 7Write protect, active on OFF position-
FPGA PUDCS1-3PUDC_BZynq MPSOC PS Config Bank 503, pin AD15ON: internal pull-up resistors enabled, OFF: floating-
SC SwitchS1-4SW4SC FPGA U18, bank 8, pin A5low active logicReserved for future use
4bit boot mode setting codeS2-1MODE3Zynq MPSOC PS Config Bank 503, pin R23Set 4-bit code for boot mode selection,
most common modes are as follows:

Set DIP-switches as bit pattern
"S1-4 | S1-3 | S1-2 | S1-1  :  Mode":

ON | ON | ON  | ON   :  JTAG Boot
ON | ON | ON  | OFF  :  Quad-SPI
ON | ON | OFF | OFF  :  SD Card

See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description

S2-2MODE2Zynq MPSOC PS Config Bank 503, pin T23
S2-3MODE1Zynq MPSOC PS Config Bank 503, pin R22
S2-4MODE0Zynq MPSOC PS Config Bank 503, pin T22
Push buttonS3USR_BTNSC FPGA U18, bank 5, pin J10low active logicSee the documentation of the firmware of SC FPGA
U18 for current functionality of the onboard Push Button S3
SC FPGA U18 Resetheader J13, pin 6M10_RSTSC FPGA U18, bank 8, pin A7low active reset line-
TEC0850 Control Signals

Signals, Interfaces, and Pins

CompactPCI Serial Backplane Connectors

The TEC0850 board is equipped with 3 CompactPCI  Serial high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface and single-ended I/O's of the System Controller FPGA.

The connectors support single-ended and differential signaling to the Zynq MPSoC PL HP banks 65 and 66 as those FPGA I/O's are routed as LVDS-pairs to the backplane connector.

The TEC0850 board is designed to be connected to the System Slot of the backplane, whereby 4 of the 6 connectors of the System Slot configuration are fitted to the TEC0850 board.

Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:

TEC0850-02 CompactPCI I/O and high-speed interfaces

Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:

  1. CompactPCI Serial Connector J1
  2. CompactPCI Serial Connector J3
  3. CompactPCI Serial Connector J4
  4. CompactPCI Serial Connector J5
  5. CompactPCI Serial Connector J6

CompactPCI Serial Connector J1

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O1-SC FPGA U18 Bank 6+3V_Dcontrol signals in cPCI pin assignment
6-SC FPGA U18 Bank 8+3V_Dcontrol signals in cPCI pin assignment
I²C2-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 I²C interface
JTAG4-SC FPGA U18 Bank 1A+3V_DSC FPGA U18 JTAG interface
MGT-8 (4 x RX/TX)Bank 502 PS GTR-4x PS GTR lanes
USB2-1 (RX/TX)USB2 PHY U11-USB2 OTG A-Device (host)
Clock Input-1Clock Driver U73-1x Reference clock input from PLL clock U14
cPCI J1 interfaces

MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
  • PE1_RX0_P
  • PE1_RX0_N
  • PE1_TX0_P
  • PE1_TX0_N



  • PE1_RX1_P
  • PE1_RX1_N
  • PE1_TX1_P
  • PE1_TX1_N


PS_MGTRRXP1_505, Y29
PS_MGTRRXN1_505, Y30

  • PE1_RX2_P
  • PE1_RX2_N
  • PE1_TX2_P
  • PE1_TX2_N


PS_MGTRRXP2_505, W31
PS_MGTRRXN2_505, W32
PS_MGTRTXP2_505, Y33
PS_MGTRTXN2_505, Y34

  • PE1_RX3_P
  • PE1_RX3_N
  • PE1_TX3_P
  • PE1_TX3_N


PS_MGTRRXP3_505, V29
PS_MGTRRXN3_505, V30
PS_MGTRTXP3_505, V33
PS_MGTRTXN3_505, V34

cPCI J1 MGT lanes

Clock Signal Schematic NamecPCI Connector PinHeader J13 PinSC FPGA U18 PinNotes



Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,
optional if decoupling capacitors and resistors
are fitted (see schematic),
also shared with SC FPGA and header J13.

cPCI J1 clock signals

CompactPCI Serial Connector J3

CompactPCI Serial connector J3 is not fitted on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2. 

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
USB2-1 (RX/TX)USB2 PHY U13-USB2 OTG A-Device (host)
cPCI J3 interfaces

CompactPCI Serial Connector J4

MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
  • PE3_RX0_P
  • PE3_RX0_N
  • PE3_TX0_P
  • PE3_TX0_N


MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30

  • PE3_RX1_P
  • PE3_RX1_N
  • PE3_TX1_P
  • PE3_TX1_N


MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32

  • PE3_RX2_P
  • PE3_RX2_N
  • PE3_TX2_P
  • PE3_TX2_N


MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30

  • PE3_RX3_P
  • PE3_RX3_N
  • PE3_TX3_P
  • PE3_TX3_N


MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30

  • PE4_RX0_P
  • PE4_RX0_N
  • PE4_TX0_P
  • PE4_TX0_N


MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

  • PE4_RX1_P
  • PE4_RX1_N
  • PE4_TX1_P
  • PE4_TX1_N


MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

  • PE4_RX2_P
  • PE4_RX2_N
  • PE4_TX2_P
  • PE4_TX2_N


MGTHRXP2_129, H33
MGTHRXN2_129, H34
MGTHTXP2_129, H29
MGTHTXN2_129, H30

  • PE4_RX3_P
  • PE4_RX3_N
  • PE4_TX3_P
  • PE4_TX3_N


MGTHRXP3_129, F33
MGTHRXN3_129, F34
MGTHTXP3_129, G31
MGTHTXN3_129, G32

  • PE5_RX0_P
  • PE5_RX0_N
  • PE5_TX0_P
  • PE5_TX0_N


MGTHRXP3_130, B33
MGTHRXN3_130, B34
MGTHTXP3_130, A31
MGTHTXN3_130, A32

  • PE5_RX1_P
  • PE5_RX1_N
  • PE5_TX1_P
  • PE5_TX1_N


MGTHRXP2_130, C31
MGTHRXN2_130, C32
MGTHTXP2_130, B29
MGTHTXN2_130, B30

  • PE5_RX2_P
  • PE5_RX2_N
  • PE5_TX2_P
  • PE5_TX2_N


MGTHRXP1_130, D33
MGTHRXN1_130, D34
MGTHTXP1_130, D29
MGTHTXN1_130, D30

  • PE5_RX3_P
  • PE5_RX3_N
  • PE5_TX3_P
  • PE5_TX3_N


MGTHRXP0_130, E31
MGTHRXN0_130, E32
MGTHTXP0_130, F29
MGTHTXN0_130, F30

  • PE6_RX0_P
  • PE6_RX0_N
  • PE6_TX0_P
  • PE6_TX0_N


MGTHRXP3_230, A4
MGTHRXN3_230, A3
MGTHTXP3_230, A8
MGTHTXN3_230, A7

  • PE6_RX1_P
  • PE6_RX1_N
  • PE6_TX1_P
  • PE6_TX1_N


MGTHRXP2_230, B2
MGTHRXN2_230, B1
MGTHTXP2_230, B6
MGTHTXN2_230, B5

  • PE6_RX2_P
  • PE6_RX2_N
  • PE6_TX2_P
  • PE6_TX2_N


MGTHRXP1_230, C4
MGTHRXN1_230, C3
MGTHTXP1_230, D6
MGTHTXN1_230, D5

  • PE6_RX3_P
  • PE6_RX3_N
  • PE6_TX3_P
  • PE6_TX3_N


MGTHRXP0_230, D2
MGTHRXN0_230, D1
MGTHTXP0_230, E4
MGTHTXN0_230, E3

cPCI J4 MGT lanes

CompactPCI Serial Connector J5

MGT LaneBankTypeSignal Schematic NamecPCI Connector PinFPGA Pin
  • PE8_RX0_P
  • PE8_RX0_N
  • PE8_TX0_P
  • PE8_TX0_N


MGTHRXP0_228, T2
MGTHRXN0_228, T1
MGTHTXP0_228, R4
MGTHTXN0_228, R3

  • PE8_RX1_P
  • PE8_RX1_N
  • PE8_TX1_P
  • PE8_TX1_N


MGTHRXP1_228, P2
MGTHRXN1_228, P1
MGTHTXP1_228, P6
MGTHTXN1_228, P5

  • PE8_RX2_P
  • PE8_RX2_N
  • PE8_TX2_P
  • PE8_TX2_N


MGTHRXP2_228, M2
MGTHRXN2_228, M1
MGTHTXP2_228, N4
MGTHTXN2_228, N3

  • PE8_RX3_P
  • PE8_RX3_N
  • PE8_TX3_P
  • PE8_TX3_N


MGTHRXP3_228, L4
MGTHRXN3_228, L3
MGTHTXP3_228, M6
MGTHTXN3_228, M5

  • PE7_RX0_P
  • PE7_RX0_N
  • PE7_TX0_P
  • PE7_TX0_N


MGTHRXP0_229, K2
MGTHRXN0_229, K1
MGTHTXP0_229, K6
MGTHTXN0_229, K5

  • PE7_RX1_P
  • PE7_RX1_N
  • PE7_TX1_P
  • PE7_TX1_N


MGTHRXP1_229, J4
MGTHRXN1_229, J3
MGTHTXP1_229, H6
MGTHTXN1_229, H5

  • PE7_RX2_P
  • PE7_RX2_N
  • PE7_TX2_P
  • PE7_TX2_N


MGTHRXP2_229, H2
MGTHRXN2_229, H1
MGTHTXP2_229, G4
MGTHTXN2_229, G3

  • PE7_RX3_P
  • PE7_RX3_N
  • PE7_TX3_P
  • PE7_TX3_N


MGTHRXP3_229, F2
MGTHRXN3_229, F1
MGTHTXP3_229, F6
MGTHTXN3_229, F5

cPCI J5 MGT lanes

PLL Clock U14 OutputSignal Schematic NamecPCI Connector J5 PinNotes
  • PE1_CLK_P
  • PE1_CLK_N


reference clock signals supplied
by on-board 10-output
PLL clock generator U14

  • PE2_CLK_P
  • PE2_CLK_N


  • PE3_CLK_P
  • PE3_CLK_N


  • PE4_CLK_P
  • PE4_CLK_N


  • PE5_CLK_P
  • PE5_CLK_N


  • PE6_CLK_P
  • PE6_CLK_N


  • PE7_CLK_P
  • PE7_CLK_N


  • PE8_CLK_P
  • PE8_CLK_N


cPCI J5 clock signals

CompactPCI Serial Connector J6

InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4623PL bank 66PL_1.8V-
189PL bank 65PL_1.8V-
2-SC FPGA U18 Bank 1B+3V_DSignalname: 'DET_RIO', 'DET_BPR'
cPCI J6 Interfaces

USB-C Connector

Front panel USB-C Interface is connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

TEC0850-02 USB3 to FIFO bridge

The USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:

InterfaceSignal Schematic NamesConnected toNotes
USB3 data lane
  • SSRX_P
  • SSRX_N

USB C Connector J10

USB2 data lane
  • SS_D_P
  • SS_D_N

USB C Connector J10

Control Lines
  • SIWU_N
  • TXE_N
  • RXF_N
  • WR_N
  • RD_N
  • OE_N
  • BE_0
  • BE_1
  • BE_2
  • BE_3

PL bank 64

Parallel GPIO's
  • DATA0
  • .
  • .
  • DATA31
PL bank 64

32bit FIFO register

USB-C connector J10

See FT600Q-FT601Q IC Datasheet for interface details.

Micro-USB2 Connector

Front panel Micro-USB2 Interface provides access to UART and JTAG functions via FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.

JTAG/UART Interface

The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:

InterfaceSignal Schematic NamesConnected toNotes
USB2 data lane
  • USB_P
  • USB_N

Micro-USB2 connector J9

Control Lines

SC FPGA U18, bank 6

Parallel GPIO's
  • ADBUS0
  • ADBUS1
  • ADBUS2
  • ADBUS3
  • BDBUS0
  • BDBUS1
  • BDBUS2
  • BDBUS3
  • BDBUS4
  • BDBUS5
  • BDBUS6
  • BDBUS7
  • BCBUS0
  • BCBUS1
  • BCBUS2
  • BCBUS3
  • BCBUS4
SC FPGA U18, bank 6


Micro-USB2 connector J9


The SD Card interface of the TEC0850 board is not directly wired to the connector J11 pins but through a Texas Instruments TXS02612 SD IO Port Expander, which is needed for voltage translation due to different voltage levels of the Micro SD Card and MIO-bank of the Xilinx Zynq MPSoC. The Micro SD Card has 3.3V signal voltage level, but the PS MIO-bank on the Xilinx Zynq MPSoC has VCCIO of 1.8V.

MicroSD Card interface

There are some limitations to use SD card Interface in Linux.

  • Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using SD IO port expander U10 as 1.8V to 3.3V level shifter. 
  • Micro SD card socket has no "Write Protect" switch.

To force Linux driver not to use these features to add following instructions to device tree file.

&sdhci1 {


RJ45 - Ethernet

Onboard Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the GbE PHY U20 status LED output.

Gigabit Ethernet Interface


On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.


Following table gives an overview of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:


Signal Schematic Name

Connected toNotes
Address inputs
  • DDR4-A0 ... DDR4-A16
PS DDR Bank 504-
Bank address inputs
  • DDR4-BA0 / DDR4-BA1
Bank group inputs
  • DDR4-BG0 / DDR4-BG1
Differential clocks
  • DDR4-CLK0_P
  • DDR4-CLK0_N
  • DDR4-CLK1_P
  • DDR4-CLK1_N
2 x DDR4 clock
Data input/output
  • DQ0 ... DQ63
Check bit input/output
  • CB0 ... CB7
Data strobe (differential)
  • DDR4-DQS0_P
  • DDR4-DQS0_N
  • ...
  • DDR4-DQS8_P
  • DDR4-DQS8_N
Data mask and data bus inversion
  • DDR4-DM0 ... DDR4-DM8
Serial address inputs
  • DDR4-SA0 ...  DDR4-SA2

address range configuration on I²C bus

Control Signals
  • DDR4-CS_N0 / DDR4-CS_N1
chip select signal
  • DDR4-ODT0 / DDR4-ODT1
On-die termination enable
  • DDR4-PAR
Command and address parity input
  • DDR4-CKE0 / DDR4-CKE1
Clock Enable
CRC error flag
  • DDR4-ACT
Activation command input
Temperature event
  • DDR4-SCL
  • DDR4-SDA
not connected-

Circular Push Pull Connector

The TEC0850 board provides 4x DAC analog voltage output on the 5-pin circular push/pull connector J15. Each of the DAC units consists of one Texas Instruments THS5641AIPW digital to analog converter, TI THS4631D operational amplifier and two LDOs, by which the DAC unit can be switched on and off.

The TI THS4631D digital to analog converter wired to the operational amplifier circuitry creating the DAC unit with a voltage output range from -0.5V ... 0.5V. See TI THS5641 datasheet and schematic how to control the DAC unit and to set the analog output voltages on connector J15.   

4x 8bit DAC units

26-Pin IDC Header

There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.   

Zynq MPSoC PL I/O's IDC pin-header

10-Pin Header

On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.

The 4 JTAG pins of the header J13 are also connected to the cPCI connector J1 and can be used as user GPIO's of the SC FPGA U18 with other functionalities then JTAG.

On the header J13, there is also a optional reference clock signal from PLL clock U14 available, if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.

10-pin JTAG/UART header

3-Pin PicoBlade Header

2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.

3-pin PicoBlade header

Battery Holder

There is a CR1220 battery holder available to the supply the voltage for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.

Backup-Battery Holder

4-Wire PWM FAN Connectors

The TEC0850 offers one 4-wire PWM FAN connector FPGA cooling fan controlled by SC FPGA U18:

4-wire PWM FAN connector

Onboard Peripherals

Zynq UltraScale XCZU15EG MPSoC

The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.

The PS MIO pins are routed to the onboard peripherals as follows:

PS MIOFunctionConnected to
1QSPI*U24-D2, DO/IO1
2QSPI*U24-C4, WP/IO2
4QSPI*U24-D3, DI/IO0 
5QSPI* U24-C2, CS
6-not connected
7QSPI*U25-C2, CS
8QSPI*U25-D3, DI/IO0
9QSPI*U25-D2, DO/IO1
10QSPI*U17-C4, WP/IO2
12QSPI*U25-B2, CLK
13 ... 15-not connected
16USB2 PHY ResetUSB2 PHY U11, pin27
17USB2 PHY ResetUSB2 PHY U13, pin27 (optional, PHY not fitted by default)
18 ... 19-not connected
20 ...21PS MIO I²CI²C peripherals
22 ... 25user MIOSC FPGA U18, bank 2
26 ... 38RGMIIGbE PHY U20
39 ... 44-not connected
45 ... 51SD IOMicroSD Card socket J11
52 ... 63USB2 ULPIUSB2 PHY U11
64 ... 75USB2 ULPIUSB2 PHY U13 (optional, PHY not fitted by default)
76 ... 77ETH MDC / MDIOGbE PHY U20

* Flash is used as QSPI dual parallel

Default MIO Configuration

MAX10 System Controller FPGA

The TEC0850 board is equipped with one System Controller FPGA (Intel MAX10 10M08SAU169C8G) with the schematic designators U18. The  SC FPGA is the central system management unit where essential control signals are logically linked by the implemented logic in FPGA firmware, which generates output signals to control the system, the onboard peripherals, and the interfaces. Interfaces like JTAG and UART between the FTDI FT2232H chip and to the Zynq MPSoC are by-passed, forwarded and controlled by the System Controller FPGA.

Other tasks of the System Controller FPGA are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depending on the SC FPGA's firmware. The documentation of the firmware of SC FPGA U18 contains detailed information on this matter.

The System Controller FPGA is connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC FPGA to control some of the onboard peripherals.

Following block diagram visualizes the connection of the SC FPGA with the Zynq Ultrascale+ MPSoC via 4 PS MIO pins (MIO22 ... 25), PS Config control signals and 10 singled ended PL HD bank 48 I/O pins (MAX_IO1 ... MAX_IO10):

TEC0850 MAX10 System Controller FPGA

Programmable Clock Generator

There is a Si5345A U14, Silicon Labs I2C programmable 10-output PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and onboard peripherals.

10-output I²C programmable clock generator

Following table shows onboard Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Si5345A U14 Pin
Signal Schematic Name
Connected toSignal DirectionNote
  • IN0_P
40.000 MHz Oscillator U75Inputexternal reference
clock input
  • IN0_N
IN1-not connectedInputnot used
-not connected


not connectedInputnot used
-not connected


not connectedInput

not used

-not connected
  • CLK0_P
Quad clock buffer
Si53340 U16

reference clock input to
Quad clock buffer

  • CLK0_N
  • PE1_CLK_N
cPCI J5, pin B5Output

reference clock output
to cPCI connector J5

  • PE1_CLK_P
cPCI J5, pin A5
  • PE5_CLK_N
cPCI J5, pin C6Output
  • PE5_CLK_P
cPCI J5, pin B6
  • PE2_CLK_N
cPCI J5, pin E5Output
  • PE2_CLK_P
cPCI J5, pin D5
  • PE3_CLK_N
cPCI J5, pin H5Output
  • PE3_CLK_P
cPCI J5, pin G5
  • PE4_CLK_N
cPCI J5, pin K5Output
  • PE4_CLK_P
cPCI J5, pin J5
  • PE6_CLK_N
cPCI J5, pin F6Output
  • PE6_CLK_P
cPCI J5, pin E6
  • PE8_CLK_N
cPCI J5, pin L6Output
  • PE8_CLK_P
cPCI J5, pin K6
  • PE7_CLK_N
cPCI J5, pin I6Output
  • PE7_CLK_P
cPCI J5, pin H6
  • CLK9_P
Clock Driver LTC6975 U73Output

reference clock input to
dual clock driver U73

  • CLK9_N
  • XAXB_P
54.000 MHz quartz
oscillator Y3
InputDifferential quartz oscillator
clock input
  • XAXB_N


  • I2C_SCL
  • I2C_SDA
  • MIO20
  • MIO21
BiDirI²C address 0x69
SI5345 Clock Outputs

The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:

Si53340 U16 Pin
Signal Schematic Name
Connected toSignal DirectionNote
  • CLK1_P
  • CLK1_N

U1, pin G8
U1, pin G7

OutputGTH bank 229 reference clock input
  • CLK2_P
  • CLK2_N

U1, pin Y8
U1, pin Y7

OutputPL HP bank 66 reference clock input
  • CLK3_P
  • CLK3_N

U1, pin U27
U1, pin U28

OutputPS GTR Bank 505 reference clock input
  • CLK4_P
  • CLK4_N

U1, pin L27
U1, pin L28

OutputGTH bank 129 reference clock input
LTC6957 U73 Pin

  • CK_PLL_P
  • CK_PLL_N

U1, pin AG5
U1, pin AG4

OutputPL HP bank 65 reference clock input
  • CK_P
  • CK_N

Signal 'SATA_SL'
Signal  'SATA_SCL'


optional reference clock input to cPCI connector J1,
if decoupling capacitors and resistors
are fitted (see schematic),
also shared with SC FPGA and header J13

Clock driver and buffer outputs

The clock generator U14 is programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

I2C addressChipDescription
0x69U14 Si5345Clock generator and distributor
SI5345 I2C address


The TEC0850 board is equipped several onboard oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the onboard peripherals with reference clock-signals:

Clock SourceSignal Schematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U22
  • PS_CLK
33.333333 MHzZynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12
  • USB0_CLK
52.000000 MHzUSB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16
  • OSCI
12.000000 MHzFTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1-30.000 MHzFTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2-32.768000 kHzZynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3
  • XAXB_P
  • XAXB_N
54.000 MHz10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21
25.000000 MHzGigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75
  • IN0_P
40.000 MHz10-output PLL clock generator U14, pin 63
TEC0850 on-board oscillators


The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.

TEC0850 on-board FTDI chips


The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx UltraScale+ Zynq SoC or Intel MAX10 (switchable over DIP) . There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the onboard JTAG will not be accessible anymore with any Xilinx tools. Software tools from the FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.

Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B is routed to are usable for example as GPIOs and other standard interfaces.

FT2232H U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0ADBUS0SC FPGA U18 bank 6, pin G9
JTAG interface
Pin 13, ADBUS1ADBUS1SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2ADBUS2SC FPGA U18 bank 6, pin E10

SC FPGA U18 bank 6, pin D9

Pin 32, BDBUS0BDBUS0SC FPGA U18 bank 6, pin B11

UART and
user configurable


Pin 33, BDBUS1BDBUS1SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2BDBUS2SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3BDBUS3SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4BDBUS4SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5BDBUS5SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6BDBUS6SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7BDBUS7SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0BCBUS0SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1BCBUS1SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2BCBUS2SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3BCBUS3SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4BCBUS4SC FPGA U18 bank 6, pin F12
Pin 11, nRESETFTDI_RSTSC FPGA U18 bank 6, pin E9control signals
FT2232H interface connections


The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also, 13 control signals of the FTDI FT601Q are connected to the HP bank 64.

FT601Q U9 PinSignal Schematic NameConnected toNotes
Pin 40, DATA0DATA0PL HP bank 64, pin AK1user GPIO's
Pin 41, DATA1DATA1PL HP bank 64, pin AJ10
Pin 42, DATA2DATA2PL HP bank 64, pin AJ9
Pin 43, DATA3DATA3PL HP bank 64, pin AK7
Pin 44, DATA4DATA4PL HP bank 64, pin AK5
Pin 45, DATA5DATA5PL HP bank 64, pin AM1
Pin 46, DATA6DATA6PL HP bank 64, pin AL2
Pin 47, DATA7DATA7PL HP bank 64, pin AK4
Pin 50, DATA8DATA8PL HP bank 64, pin AN1
Pin 51, DATA9DATA9PL HP bank 64, pin AL3
Pin 52, DATA10DATA10PL HP bank 64, pin AK8
Pin 53, DATA11DATA11PL HP bank 64, pin AN2
Pin 54, DATA12DATA12PL HP bank 64, pin AP2
Pin 55, DATA13DATA13PL HP bank 64, pin AL7
Pin 56, DATA14DATA14PL HP bank 64, pin AL5
Pin 57, DATA15DATA15PL HP bank 64, pin AM4
Pin 60, DATA16DATA16PL HP bank 64, pin AN4
Pin 61, DATA17DATA17PL HP bank 64, pin AM5
Pin 62, DATA18DATA18PL HP bank 64, pin AM6
Pin 63, DATA19DATA19PL HP bank 64, pin AN3
Pin 64, DATA20DATA20PL HP bank 64, pin AP3
Pin 65, DATA21DATA21PL HP bank 64, pin AP4
Pin 66, DATA22DATA22PL HP bank 64, pin AP5
Pin 67, DATA23DATA23PL HP bank 64, pin AN6
Pin 69, DATA24DATA24PL HP bank 64, pin AN7
Pin 70, DATA25DATA25PL HP bank 64, pin AP6
Pin 71, DATA26DATA26PL HP bank 64, pin AP7
Pin 72, DATA27DATA27PL HP bank 64, pin AP11
Pin 73, DATA28DATA28PL HP bank 64, pin AP10
Pin 74, DATA29DATA29PL HP bank 64, pin AP9
Pin 75, DATA30DATA30PL HP bank 64, pin AN9
Pin 76, DATA31DATA31PL HP bank 64, pin AP8
Pin 58, CLKFIFO_CLKPL HP bank 64, pin AL6control signals
Pin 4, BE0BE_0PL HP bank 64, pin AM10
Pin 5, BE1BE_1PL HP bank 64, pin AK10
Pin 6, BE2BE_2PL HP bank 64, pin AM11
Pin 7, BE3BE_3PL HP bank 64, pin AL11
Pin 13, nOEOE_NPL HP bank 64, pin AL8
Pin 12, nRDRD_NPL HP bank 64, pin AK9
Pin 11, nWRWR_NPL HP bank 64, pin AM9
Pin 8, nTXETXE_NPL HP bank 64, pin AK12
Pin 9, nRXNRXF_NPL HP bank 64, pin AJ12
Pin 10, nSIWUSIWU_NPL HP bank 64, pin AL10
Pin 15, nRESETFTDI_RESET_NPL HP bank 64, pin AM8
Pin 16, nWAKEUPWAKEUP_NPL HP bank 64, pin AN8
FT601Q interface connections

Quad-SPI Flash Memory

On-board QSPI flash memory U24 and U25 on the TEC0850 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each, 64 MByte total QSPI Flash memory. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC, enabling dual parallel booting from QSPI Flash memory. This nonvolatile memory is used to store an initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad-SPI Flash Memory

ICMemory DensityMIOSignal Schematic NameFlash Memory Pin

QSPI Flash U24,


256 Mbit (32 MByte)0













QSPI Flash U25,


256 Mbit (32 MByte)7


Quad-SPI Flash memory interface connections


The TEC0850 board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces are connected to Zynq MPSoC bank 502 MIO 20...21 pins:

On-board configuration EEPROMs

The EEPROMs U63 and U64 are programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

I2C addressChipDescription
0x50U63 24AA128T-I/ST128K Serial EEPROM
0x53U64 24AA025E48T-I/OT2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity
EEPROMs I²C Addresses


USB2 PHY U11 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U12. There is also the option to equip the TEC0850 board with a second USB2 PHY U13 connected to the optional cPCI backplane connector J3. Both, the optional USB2 PHY U13 and cPCI connector J3 are not fitted by default.

TEC0850 cPCI USB2 interface

USB2 PHY U11 PinConnected toNotes
ULPIPS bank MIO52 ... MIO63Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK-52MHz from onboard oscillator U12
REFSEL[0..2]-All pins set to GND selects the external reference clock frequency (52.000000 MHz)

Zynq MPSoC MIO16, pin AM16

Low active USB2 PHY Reset
DP, DMcPCI connector J1USB2 data lane
CPEN-External USB power switch active-high enable signal
VBUS5VConnected to onboard 5V voltage level via a series of resistors, see schematic
ID3.3VUSB2 OTG A-Device (host)
optional USB2 PHY U13 PinConnected toNotes
ULPIPS bank MIO64 ... MIO75Zynq Ultrascale+ USB1 MIO pins are connected to the PHY
REFCLK-52MHz from onboard oscillator U12
REFSEL[0..2]-All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETBZynq MPSoC MIO17, pin AP16Low active USB2 PHY Reset
DP, DMoptional cPCI connector J3USB2 data lane
CPEN-External USB power switch active-high enable signal
VBUS5VConnected to onboard 5V voltage level via a series of resistors, see schematic
ID3.3VUSB2 OTG A-Device (host)
USB2 ULPI interface description

Gigabit Ethernet PHY

Onboard Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512, which use MDIO address 1. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.

TEC0850 GbE interface with RJ-45 MegJack

8bit DACs

The TEC0850 Board has 4 8-bit parallel  Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.

DAC unitSignal Schematic NameConnected toFunctionality




PL HD bank 50, pin D11

Digital input bits D[7:0]

D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).


PL HD bank 50, pin D10


PL HD bank 50, pin G11


PL HD bank 50, pin J11


PL HD bank 50, pin G10


PL HD bank 50, pin H10

DAC1_D6PL HD bank 50, pin J10
DAC1_D7PL HD bank 50, pin E10
DAC1_CLKPL HD bank 50, pin F12External clock input, input data latched on rising edge of the clock.
DAC1_MODEPL HD bank 50, pin F10Input code format (binary, twos complement)
EN_DAC1SC FPGA U18 bank 8, pinE6generate 3.3V voltages
LDO U35, U34



DAC2_D0PL HD bank 50, pin G15

Digital input bits D[7:0]

D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).


PL HD bank 50, pin H14


PL HD bank 50, pin J14

DAC2_D3PL HD bank 50, pin G14
DAC2_D4PL HD bank 50, pin G13
DAC2_D5PL HD bank 50, pin H13
DAC2_D6PL HD bank 50, pin H12
DAC2_D7PL HD bank 50, pin J12
DAC2_CLKPL HD bank 50, pin F12
External clock input, input data latched on rising edge of the clock.
DAC2_MODEPL HD bank 50, pin F11
Input code format (binary, twos complement)
EN_DAC2SC FPGA U18 bank 8, pin E8
generate 3.3V voltages
LDO U32, U60



DAC3_D0PL HD bank 44, pin AG14

Digital input bits D[7:0]

D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC3_D1PL HD bank 44, pin AE13
DAC3_D2PL HD bank 44, pin AG13
DAC3_D3PL HD bank 44, pin AJ15
DAC3_D4PL HD bank 44, pin AJ14
DAC3_D5PL HD bank 44, pin AH14
DAC3_D6PL HD bank 44, pin AL13
DAC3_D7PL HD bank 44, pin AM13
DAC3_CLKPL HD bank 44, pin AK15
External clock input, input data latched on rising edge of the clock.
DAC3_MODEPL HD bank 44, pin AK14
Input code format (binary, twos complement)
EN_DAC3SC FPGA U18 bank 8, pin B6
generate 3.3V voltages
LDO U66, U68



DAC4_D0PL HD bank 44, pin AP14

Digital input bits D[7:0]

D7 is the most significant data bit (MSB),
D0 is the least significant data bit (LSB).

DAC4_D1PL HD bank 44, pin AN14
DAC4_D2PL HD bank 44, pin AM14
DAC4_D3PL HD bank 44, pin AN13
DAC4_D4PL HD bank 44, pin AP12
DAC4_D5PL HD bank 44, pin AN12
DAC4_D6PL HD bank 44, pin AF13
DAC4_D7PL HD bank 44, pin AH13
DAC4_CLKPL HD bank 44, pin AK13
External clock input, input data latched on rising edge of the clock.
DAC4_MODEPL HD bank 44, pin AK13Input code format (binary, twos complement)
EN_DAC4SC FPGA U18 bank 8, pin A6
generate 3.3V voltages
LDO U70, U72
DAC units interface description


There are two 4-bit DIP-witches S3 and S4 present on the TEC0850 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

The table below describes the functionalities of the switches of DIP-switches S1 and S2 at their every position:

DIP-switch S1Signal Schematic NameConnected toFunctionalityNotes


SC FPGA U18, bank 1B, pin E5

OFF: SC FPGA's JTAG enabled
ON: Zynq MPSoC's JTAG enabled

to switch the JTAG interface between SC FPGA and Zynq MPSoC


EEPROM U63, pin 7

OFF: Write Protect is enabled
ON: Write Protect is disabled



Zynq MPSOC PS Config Bank 503, pin AD15

ON: PUDC_B is Low

Internal pull-up resistors during configuration
are enabled at ON-position, means I/O's are 3-stated
until the configuration of the FPGA completes.



SC FPGA U18, bank 8, pin A5SC Switch (Reserved for future use)low active logic
DIP-switch S2Signal Schematic NameConnected toFunctionalityNotes


Zynq MPSOC PS Config Bank 503, pin R23

set 4-bit code for boot mode selection

See Zynq UltraScale+ Device Technical Reference Manual
page 236 for full boot modes description

Set DIP-switches as bit pattern of S2

BOOT Mode1234



Zynq MPSOC PS Config Bank 503, pin T23



Zynq MPSOC PS Config Bank 503, pin R22



Zynq MPSOC PS Config Bank 503, pin T22

TEC0850 DIP-switches description


There is one switch button available to the user connected to the SC FPGA U18:

ButtonSignal Schematic NameConnected toNotes
S3USR_BTNSC FPGA U18, bank 5, pin J10

low active logic

Refer documentation of the firmware of SC FPGA U18.

On-board Push-Button


The TEC0850 board is equipped with several LEDs to signal current states and activities.

LEDColorConnected toDescription and Notes
Front panel LED D1RedZynq MPSoC PL bank 11, pin AF15PL User defined LED
Front panel LED D2GreenZynq MPSoC PL bank 11, pin AG15PL User defined LED
Front panel LED D3GreenZynq MPSoC PL bank 11, pin AE15PL User defined LED
Front panel LED D4GreenSC FPGA U18 bank 3, pin M4Power Good
On-board LEDs description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provides a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
Typical power consumption

Power supply with a minimum current capability of 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.

The TEC0850 board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet an embedded system power management requirement by advanced power management features. These features allow offsetting the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.

The Processing System contains three Power Domains:

  • Battery Power Domain (BBRAM and RTC)
  • Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
  • Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
  • Programmable Logic (PL)

Power Distribution Dependencies

There are following dependencies how the initial 24V voltage from the main power pins on cPCI slot J1 is distributed to the onboard DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Power Distribution

Power-On Sequence

The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the onboard DC-DC converters dedicated to the particular Power Domains and powering up the onboard voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller FPGA U18:

  1. Main Power and Programmable Logic (PL)
  2. Low-Power Domain (LPD)
  3. Full-Power Domain (FPD)
  4. GTH, PS GTR transceiver and DDR memory
  5. Optional DAC voltages

Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance are asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Power-On Sequence Diagram
To avoid any damage to the MPSoC module, check for stabilized onboard voltages in a steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during the power-on sequence.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all onboard voltages have become stable and the module is properly powered up.

See Xilinx datasheet DS925 for additional information.

Voltage Monitor Circuit

The voltages PS_1V8 and VCCINT_0V85 are monitored by the voltage monitor circuit U69, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the low active MR-pin connected to MAX10 FPGA U18 (bank5, pin K10) to GND.

Voltage monitor circuit

Power Rails

Connector / PinVoltageDirectionNotes
J1, pin A1, D1, E1, G1, H1, J1, K1VIN_12VInputMain power supply pins
J17, pin 212VOutput4-wire PWM fan connector supply voltage
J13, pin 4+3V_DOutputJTAG/UART reference VCCIO voltage
B1, pin +VBATTInput3.0V CR1220 battery
J16, pin 25VOutputI/O header VCCIO
J16, pin 13.3VOutputI/O header VCCIO
J9, pin 4VBUSInputUSB2 VBUS (5.0V nominal)
J10, pin A4, B9VBUS30InputUSB3 VBUS (5.0V nominal)
J11, pin 43.3VOutputMicroSD Card VDD
J15, pin 2DAC1_OUTOutputDAC output
J15, pin 3DAC2_OUTOutputDAC output
J15, pin 4DAC3_OUTOutputDAC output
J15, pin 5DAC4_OUTOutputDAC output
TEC0850 power rails description

Bank Voltages

Zynq MPSoC BankTypeSchematic NameVoltageVoltage Range
44HD3.3V3.3Vfixed to 3.3V
47HD3.3V3.3Vfixed to 3.3V
48HD3.3V3.3Vfixed to 3.3V
49HD3.3V3.3Vfixed to 3.3V
50HD3.3V3.3Vfixed to 3.3V
64HPPL_1V81.8Vfixed to 1.8V
65HPPL_1V81.8Vfixed to 1.8V
66HPPL_1V81.8Vfixed to 1.8V
67HPPL_1V81.8Vfixed to 1.8V
500MIOPS_1V81.8Vfixed to 1.8V
501MIOPS_1V81.8Vfixed to 1.8V
502MIOPS_1V81.8Vfixed to 1.8V
503CONFIGPS_1V81.8Vfixed to 1.8V


fixed bank voltages











fixed bank voltages











fixed bank voltages
MAX10 FPGA BankTypeSchematic NameVoltageVoltage Range
1A-+3V_D3.3Vfixed to 3.3V
1B-+3V_D3.3Vfixed to 3.3V
2-PS_1V81.8Vfixed to 1.8V
3-3.3V3.3Vfixed to 3.3V
5-+3V_D3.3Vfixed to 3.3V
6-+3V_D3.3Vfixed to 3.3V
8-+3V_D3.3Vfixed to 3.3V
TEC0850 Zynq MPSoC and SC FPGA bank voltages

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN_12V-0.316VIntel Enpirion EM2130 data sheet / Fuse F1Fuse F1 @16V/2.5A
VBATT-0.36VTPS780180300 data sheet1.8V typical output
VCCO for HD I/O banks-0.53.4VXilinx document DS925-
VCCO for HP I/O banks-0.52VXilinx document DS925-
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx document DS925-
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx document DS925-
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx document DS925VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925-
PS GTR absolute input voltage-0.51.1VXilinx document DS925-
MGT clock absolute input voltage-0.51.3VXilinx document DS925-

MGT Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx document DS925-

SC FPGA U18 I/O input voltage

-0.5VCC + 0.5VIntel MAX 10 data sheetVCC 3.3V nominally
A voltage on input I/O pins of DC-DC U17 EM2130
on header J12
-0.33.6VIntel Enpirion EM2130 datasheet-

Storage temperature (ambient)




ASVTX-12 datasheet-
Module absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitReference DocumentNotes
VIN_12V1214VIntel Enpirion EM2130 datasheet12V nominally input voltage
VBATT2.25.5VTPS780180300 data sheetsupplied by 3.0V CR1220 battery
VCCO for HD I/O banks1.143.4VXilinx document DS925-
VCCO for HP I/O banks0.951.9VXilinx document DS925-
I/O input voltage for HD I/O banks-0.2VCCO + 0.2VXilinx document DS925-
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx document DS925-
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx document DS925VCCO_PSIO 1.8V nominally
SC FPGA U18 I/O input voltage0VCCV

Intel MAX 10 data sheet

VCC 3.3V nominally
Board Operating Temperature Range 1), 2)085°CXilinx document DS925extended grade Zynq MPSoC temperature range
Module absolute maximum ratings

1) Temperature range may vary depending on assembly options

2) The operating temperature range of the Zynq MPSoC, SC FPGA SoC and onboard peripherals are a junction and also ambient operating temperature ranges

Physical Dimensions

Physical dimensions drawing

Variants Currently In Production

Trenz shop TE0xxx overview page
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Shop Overview

Revision History

Hardware Revision History

DateRevisionPCNDocumentation LinkNotes


-TEC0850-02current available board revision
Module hardware revision history

Document Change History


  • boot mode bugfix
2018-10-26v.103John Hartfiel
  • change" Compact PCI" to "Compact PCI Serial"

v.102Ali Naseri
  • small corrections


John Hartfiel

  • style changes

v.97Ali Naseri
  • added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)


John Hartfiel

  • small style changes and typo correction

v.93 Ali Naseri , Oleksandr Kiyenko , John Hartfiel
  • initial release
  • --
Document change history


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