Table of contents


TEC0850 design for MAX10 FPGA U18:  10M08SAU169C8G.

Feature Summary

  • SC to HD-IO Bank Interface
  • I²C Backplane interface
  • I²C System Control interface
  • Power control
  • Power status
  • FAN Control
  • FAN Status
  • Power status indication

Firmware Revision and supported PCB Revision

See Document Change History.

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription
ADBUS0        inG93V_DFTDI TCK
ADBUS1        inF103V_DFTDI TDI
ADBUS2        outE103V_DFTDI TDO
ADBUS3        inD93V_DFTDI TMS
AVDD_SHDN     inoutG103V_DAVDD Shutdown / AVDD OV/UV
BCBUS0        -D123V_DFTDI (JTAG/UART, U4) / currently_not_used
BCBUS1        -E133V_DFTDI (JTAG/UART, U4) currently_not_used
BCBUS2        -E123V_DFTDI (JTAG/UART, U4) currently_not_used
BCBUS3        -F133V_DFTDI (JTAG/UART, U4) currently_not_used
BCBUS4        -F123V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS2        -B123V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS3        -C113V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS4        -B133V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS5        -C123V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS6        -C133V_DFTDI (JTAG/UART, U4) currently_not_used
BDBUS7        -D113V_DFTDI (JTAG/UART, U4) currently_not_used
CONF_DONE     -C53V_Dcurrently_not_used
DET_BPR       -H23V_Dcurrently_not_used
DET_RIO       -H33V_Dcurrently_not_used
DONE          inN3PS_1V8FPGA Done
EN_3V3        outC103V_D3.3V Power Enable
EN_DAC1       outE63V_DDAC1 Power Enable
EN_DAC2       outE83V_DDAC2 Power Enable
EN_DAC3       outB63V_DDAC3 Power Enable
EN_DAC4       outA63V_DDAC4 Power Enable
EN_DDR        outG133V_DDDR Power Enable
EN_FPD        outL123V_DFPD Power Enable
EN_LPD        outJ133V_DLPD Power Enable
EN_PSGT       outB93V_DPSGT Power Enable
ERR_OUT       -G5PS_1V8currently_not_used
ERR_STATUS    -H6PS_1V8currently_not_used
F_TCK         outN2PS_1V8FPGA TCK
F_TDI         outM1PS_1V8FPGA TDI
F_TDO         inK1PS_1V8FPGA TDO
F_TMS         outJ1PS_1V8FPGA TMS
F1PWM         outH103V_DFAN PWM Control
F1SENSE       inJ93V_DFAN Sense
FTDI_RST      outE93V_DFTDI Reset
GA0           -F83V_DBackplane address / currently_not_used
GA0_R         -F93V_DBackplane address, pullup/down enable currently_not_used
GA1           -A23V_DBackplane addresscurrently_not_used
GA1_R         -B23V_DBackplane address, pullup/down enable currently_not_used
GA2           -A33V_DBackplane addresscurrently_not_used
GA2_R         -B33V_DBackplane address, pullup/down enable currently_not_used
GA3           -A43V_DBackplane addresscurrently_not_used
GA3_R         -B43V_DBackplane address, pullup/down enable currently_not_used
IEEE_SW_NC    -C93V_Dcurrently_not_used
IEEE_SW_NO    -A113V_Dcurrently_not_used
INIT_B        inL2PS_1V8FPGA Init
JTAGEN        -E53V_DJTAG Enable
LED_FP_4      outM43.3VFront panel LED
LP_GOOD       inH133V_DLP Power Good
M10_RST       -A73V_Dcurrently_not_used
M10_RX        -C23V_Dcurrently_not_used
M10_TX        -B13V_Dcurrently_not_used
MAX_IO1 / IO1    inN83.3VI²C SCL in, ZynqMP Pin G18
MAX_IO10      -M103.3Vcurrently_not_used
MAX_IO2 / IO2 outN73.3VI²C SCL out, ZynqMP Pin G19
MAX_IO3 / IO3 inM93.3VI²C SDA in, ZynqMP Pin K18
MAX_IO4 / IO4 outM83.3VI²C SDA out, ZynqMP Pin H19
MAX_IO5 / IO5 inM123.3VUser LED in, ZynqMP Pin J17
MAX_IO6       -M133.3Vcurrently_not_used
MAX_IO7       -N93.3Vcurrently_not_used
MAX_IO8       -N103.3Vcurrently_not_used
MAX_IO9       -M113.3Vcurrently_not_used
MIO22         outM3PS_1V8UART out
MIO23         inM2PS_1V8UART in
MIO24         -L3PS_1V8currently_not_used
MIO25         -H5PS_1V8currently_not_used
MR            outK103V_DSupervisor Reset out
nCONF         -E73V_Dcurrently_not_used
nSTATUS       -C43V_Dcurrently_not_used
ON_GT_L       outJ123V_DGT_L Power Enable
ON_GT_R       outK123V_DGT_R Power Enable
PG_DDR        inH83V_DDDR Power Good
PG_GT_L       inH93V_DGT_L Power Good
PG_GT_R       inG123V_DGT_R Power Good
PG_PL         inL133V_DPL Power Good
PG_PSGT       inK113V_DPSGT Power Good
PLL_RST       outK2PS_1V8PLL Chip Reset
PROG_B        outJ2PS_1V8FPGA PROG_B
PSON          -D63V_Dcurrently_not_used
RP_SCL        -E13V_Dcurrently_not_used
RP_SDI        -G43V_Dcurrently_not_used
RP_SDO        -F43V_Dcurrently_not_used
RP_SL         -F13V_Dcurrently_not_used
RST           -B53V_Dcurrently_not_used
RST_PRST      -A83V_Dcurrently_not_used
RST_PRST_R    -B103V_Dcurrently_not_used
RST_R         -D83V_Dcurrently_not_used
SATA_SCL      -G23V_Dcurrently_not_used
SATA_SDI      -F63V_Dcurrently_not_used
SATA_SDO      -F53V_Dcurrently_not_used
SATA_SL       -G13V_Dcurrently_not_used
SMB_SCL       inoutE33V_DI²C SCL
SMB_SCL_R     outE43V_DI²C SCL Pullup Enable
SMB_SDA       inoutC13V_DI²C SDA
SMB_SDA_R     outD13V_DI²C SDA Pullup Enable
SRST_B        outH4PS_1V8FPGA SRST_B
SW4           inA53V_DDip Switch
SYSEN         -D73V_Dcurrently_not_used
USR_BTN       inJ103V_DFront panel button
WAKE          -A93V_Dcurrently_not_used
WAKE_R        -A103V_Dcurrently_not_used

Functional Description


System Controller provides control and status information for main power rails. By default all power rails are ON, the user can manipulate power using I²C interface, see  Memory map table.


System controller generates a reset pulse to supervisor chip U69 when front panel button S3 is pressed.


JTAG interface from FTDI controller passes through System Controller to FPGA.

I²C Interface

To use SC I²C interface corresponding connection should be configured in the FPGA project. There are 2 standard I²C interface controllers, which can be used AXI_IIC or Zynq UltraScale+ MPSoC integrated I²C controller.


Zynq UltraScale+ MPSoC integrated I²C controller

Project XDC file should contain

set_property PACKAGE_PIN G18 [get_ports {MAX_IO1}]
set_property PACKAGE_PIN G19 [get_ports {MAX_IO2}]
set_property PACKAGE_PIN K18 [get_ports {MAX_IO3}]
set_property PACKAGE_PIN H19 [get_ports {MAX_IO4}]
set_property IOSTANDARD LVCMOS33 [get_ports MAX_IO*]
set_property PULLUP true [get_ports {MAX_IO2}]
set_property PULLUP true [get_ports {MAX_IO4}]

With this configuration, I²C device with address 0x20 should be visible on I²C bus

This device is an emulation of TCA6416 I²C GPIO Chip. GPIO input and output pins are used to get status and control the system.

Memory map

0Input Port 0

Power status register:

Bit 0 - LP_PGOOD

Bit 1 - PG_PL

Bit 2 - PG_PSGT

Bit 3 - PG_GT_L

Bit 4 - PG_GT_R

Bit 5 - PG_DDR

Bit 6 - AVDD OV/UV

Bit 7 - Not Used "0"

1Input Port 1

FAN Status register

Bits 7:0 - FAN RPM/1000

(Nominal Sepa HFB44B-12A speed is 8000 RPM)

2Output Port 0

Control register 0

Bits 1:0 - LED Control (Default "01")

Bit 2 - SMB Strong Pull-Up Enable (Default "1")

Bit 3 - Enable DAC1 Power (Default "1")

Bit 4 - Enable DAC2 Power (Default "1")

Bit 5 - Enable DAC3 Power (Default "1")

Bit 6 - Enable DAC4 Power (Default "1")

Bit 7 - Enable FPD Power (Default "1")

3Output Port 1

Control register 1

Bit 0 - Enable LPD Power (Default "1")

Bit 1 - Enable DDR Power (Default "1")

Bit 2 - Enable PSGT Power (Default "1")

Bit 3 - Enable GT_L Power (Default "1")

Bit 4 - Enable GT_R Power (Default "1")

Bit 5 - Enable FAN Power (Default "1") (Works only if 4-wire FAN is used)

Bit 6 - Enable AVDD Power (Default "1")

Bit 7 - System reset (Default "0", Reset by rising edge)

LED Control

Bits [1:0]Mode
"00"LED4 is OFF
"01"LED4 is Power indicator
"10"LED4 is User LED (connected to IO5)
"11"LED4 is ON

Power Indicator

OFFNo power or SC failure
1 Pulse (*ooooooo)PSGT Power is not OK
2 Pulses (**oooooo)DDR Power is not OK
3 Pulses (***ooooo)LP Power is not OK
4 Pulses (****oooo)GT_L Power is not OK
5 Pulses (*****ooo)

GT_R Power is not OK

6 Pulses (******oo)PL Power is not OK
ONNo power problems detected

I²C GPIO registers can be operated with  directly, using Linux i2cset and i2cget commands

root@petalinux:~# # Disable LED4
root@petalinux:~# i2cset -y 0 0x20 2 0xFC
root@petalinux:~# # Get Power status
root@petalinux:~# i2cget -y 0 0x20 0 b
root@petalinux:~# # Get FAN RPM/1000
root@petalinux:~# i2cget -y 0 0x20 1 b

or I²C GPIO device driver can be instantiate in Linux device tree (project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi).

&i2c0 {
	tca6416: tca6416@21 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		#gpio-cells = <2>;


The System Controller control D4 LED (front panel green rightmost LED). By default, it act like power status indicator see "Power Indicator" table in "I²C interface" section.

Appx. A: Change History and Legal Notices

Revision Changes

RE02 to REV03

  • Add I²C GPIO core
  • FAN Control/FAN Status
  • Power control

RE03 to REV04

  • BUGFIX Reset

Document Change History

To get content of older revision got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

  • REV04 finished
  • Firmware release on 2018-10-24
2018-10-10v.20REV03REV02Oleksandr Kiyenko
  • REV03 finished
  • Firmware release on 2018-10-10
2018-08-15v.3REV02REV02Antti Lukats
  • initial release


Appx. A: Legal Notices

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