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anchor | Figure_10 |
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title | Figure 10: Zynq MPSoC PL I/O's IDC pin-header |
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diagramName | TEC0850 header J16 |
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On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as reference I/O-voltage for JTAG and UART.
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anchor | Figure_14 |
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title | Figure 14: 4-wire PWM FAN connectorsconnector |
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diagramName | TEC0850 4-Wire PWM Connector |
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The PS MIO pins are routed to the on-board peripherals as follows:
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anchor | Table_x13 |
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title | Table x13: Default MIO Configuration |
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orientation | portrait |
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PS MIO | Function | Connected to |
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0 | SPI0 | U24-B2, CLK |
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1 | SPI0 | U24-D2, DO/IO1
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2 | SPI0 | U24-C4, WP/IO2
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3 | SPI0 | U24-D4, HOLD/IO3 |
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4 | SPI0 | U24-D3, DI/IO0 |
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5 | SPI0 | U24-C2, CS |
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6 | - | Not connected |
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7 | SPI1 | U25-C2, CS |
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8 | SPI1 | U25-D3, DI/IO0 |
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9 | SPI1 | U25-D2, DO/IO1 |
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10 | SPI1 | U17-C4, WP/IO2 |
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11 | SPI1 | U25-D4, HOLD/IO3 |
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12 | SPI1 | U25-B2, CLK |
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13 ... 15 | - | not connected |
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16 | USB2 PHY Reset | USB2 PHY U11 |
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17 | - | not used |
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18 ... 19 | - | not connected |
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20 ...21 | PS MIO I²C | I²C peripherals |
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22 ... 25 | user MIO | SC FPGA U18, bank 2 |
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26 ... 38 | RGMII | GbE PHY U20 |
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39 ... 44 | - | not connected |
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45 ... 51 | SD IO | MicroSD Card socket J11 |
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52 ... 63 | USB2 ULPI | USB2 PHY U11 |
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64 ... 75 | - | not used |
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76 ... 77 | ETH MDC / MDIO | GbE PHY U20 |
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