changes.mady.by.user Ali Naseri
Saved on 14 09, 2018
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J1-K3J1-J3
J13-5J13-1
Bank 1B, Pin G1Bank 1B, Pin G2
Supplied by 10-output PLL clock U14,
cPCI connector J1 clock signal from PLL U14 isalso shared with SC FPGA and header J13
J1-A1J1-D1J1-E1J1-G1J1-H1J1-J1J1-K1
cPCI backplane
min. cur.: 6.65A