DIP-switch S1 | Signal Schematic Name | Connected to | Functionality | Notes |
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S1-1 | JTAGEN | SC FPGA U18, bank 1B, pin E5 | Positions: OFF: SC FPGA's JTAG enabled ON: Zynq MPSoC's JTAG enabled | switch the JTAG interface between SC FPGA and Zynq MPSoC |
S1-2 | WP | EEPROM U63, pin 7 | Positions: OFF: Write Protect is enabled ON: Write Protect is disabled | - |
S1-3 | PUDC_B | Zynq MPSOC PS Config Bank 503, pin AD15 | Positions: ON: PUDC_B is Low OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position,means I/O's are 3-stated until configuration of the FPGA completes. |
S1-4 | SW4 | SC FPGA U18, bank 8, pin A5 | SC Switch (Reserved for future use) | low active logic |
DIP-switch S2 | Signal Schematic Name | Connected to | Functionality | Notes |
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S2-1 | MODE3 | Zynq MPSOC PS Config Bank 503, pin R23 | set 4-bit code for boot mode selection | See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description
Set DIP-switches as as bit pattern "S1-4 | S1-3 | S1-2 | S1-1 : Boot Mode": ON | ON | ON | ON : JTAG Boot Mode ON | ON | ON | OFF : Quad-SPI ON | ON | OFF | OFF : SD Card |
S2-2 | MODE2 | Zynq MPSOC PS Config Bank 503, pin T23 |
S2-3 | MODE1 | Zynq MPSOC PS Config Bank 503, pin R22 |
S2-4 | MODE0 | Zynq MPSOC PS Config Bank 503, pin T22 |