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Initial Delivery State

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title	Table 1: Initial delivery state of programmable devices on the module.

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Storage device name	Content	Notes
SPI Flash OTP Area	Empty, not programmed	Except serial number programmed by flash vendor
SPI Flash Quad Enable bit	Programmed
SPI Flash main array	demo design
eFUSE USER	Not programmed
eFUSE Security	Not programmed

Control Signals

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Overview of Boot Mode, Reset, Enables,

Boot process is controlled by signals on the board to board (B2B) connector.

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title	Table 2: Boot signals.

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Signal	Direction	Signal State	Description
BOOTMODE	input	high or open	Master SPI, x4 Mode
BOOTMODE	input	low or ground	Slave SelectMAP
PROG_B	input	pulsed low	Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).
DONE	output	high	Completion of configuration sequence.

Note
SPI FPGA pins D02 and D03 have no pull-ups on the module, so with PUDC=High option, those pins are floating if there are no pull-ups on baseboard. As those pins have SPI RESET function when Quad mode is not enabled, it is mandatory to either add pull-ups on user baseboard or program the Quad Enable bit in Flash nonvolatile status register.

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title	Table 3: JTAG signals.

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Signal Name	B2B Pin
TCK	JM1:89
TDI	JM1:85
TDO	JM1:87
TMS	JM1:91

On-board LED's

There is one LED on TE0714 module:

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title	Table 4: LED connection.

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LED	Color	FPGA	Notes
D4	Red	K18

Clock

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title	Table 5: Clock signals.

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Clock	Default Frequency	IC	FPGA	Notes
CLK25MHz	25 MHz	U8	T14	Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK	125MHz	U2	B6/B5	Frequency depends on the module variant

Board to Board (B2B) I/Os

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title	Table 6: B2B I/Os

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FPGA Bank	B2B Connector	I/O Signal Count	Voltage Level	Notes
14	JM1	6	VCCIO_0
14	JM2	36	VCCIO_0	NB! 17 LVDS pairs possible.
15	JM2	48	VCCIO15	Supplied by the baseboard.
34	JM1	48	VCCIO34	Supplied by the baseboard.
216	JM1	16	MGT_AVCC MGT_AVTT	4 x GTP lanes.

Please refer to the Pin-out tables page for additional information.

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title	Table 7: Power Consumption

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Test Condition (25 °C ambient)	VIN Current mA	Notes
TE0714-35, TEBT0714, empty design, GT not enabled	110mA

Actual power consumption depends on the FPGA design and ambient temperature.

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There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.

Power Rails

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title	Table 8: Power Rails

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Voltages on B2B- Connector	B2B JM1-Pin	B2B JM1-Pin	Direction	Note
VIN	98, 100	-	input	supply voltage
VCCIO_0	-	54	input	high range bank voltage
VCCIO_15	-	53	input	high range bank voltage
VCCIO_34	62	-	input	high range bank voltage
3.3V	84	-	output	internal 3.3V voltage level
1.8V	-	17	output	internal 1.8V voltage level

Bank Voltages

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title	Table 89: Bank Voltages

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Bank	Voltage	Notes
0 Config and B14	1.8V or 3.3V	Depends on module variant
15	User	Supplied from baseboard via B2B connector, max 3.3V
34	User	Supplied from baseboard via B2B connector, max 3.3V

Board to Board Connectors

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Absolute Maximum Ratings

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title	Table 910: Module absolute maximum ratings.

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.1	6.0	V	-
HR I/O banks supply voltage (VCCO)	-0.5	3.6	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.4	VCCO + 0.55	V	Xilinx datasheet DS181
GTP transceivers Tx/Rx input voltage	-0.5	1.26	V	Xilinx datasheet DS181
Voltage on module JTAG pins	-0.4	VCCO_0 + 0.55	V	Xilinx datasheet DS181
Storage temperature	-40	+85	°C	-

Recommended Operating Conditions

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title	Table 1011: Recommended Operating Conditions

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.135	3.45	V	-
HR I/O banks supply voltage (VCCO)	1.14	3.465	V	Xilinx datasheet DS181
HR I/O banks input voltage	-0.20	VCCO + 0.20	V	Xilinx datasheet DS181
Voltage on module JTAG pins	3.135	3.465	V	Xilinx datasheet DS181

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Weight

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title	Table 1112: Module Wight

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Variant	Weight in g	Note
2IC6	8.3	Plain Module

Variants Currently In Production

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Set correct link to the shop page overview table of the product on English and German, if not available, set
- https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/
- https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/

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title	Table 1213: Trenz Electronic Shop Overview

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Trenz shop TE0714 overview page
English page	German page

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Hardware Revision History

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title	Table 1314: Module absolute maximum ratings.

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Date	Revision	Note	PCN	Documentation Link
2018-11-01	02	Replaced Replace obsolete SPI Flash	in preparation	TE0714-02
2016-08-04	02	VCCIO0 added to B2B	PCN-20160815	TE0714-02
	01	-	-	TE0714-01

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Date

Revision

Authors

Description

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Added power rail section
Added Rev 02 Flash PCN
corrected table headings

2018-09-17

v.36

Martin Rohrmüller

Update to TRM version 2.0 with DrawIO Figures
Added Figure Power Distribution

2018-04-04

v.35

Martin Rohrmüller

Corrected clock net designator in table.

2017-05-28

V.27

Jan Kumann

Board-to-Board I/O section added.

New physical dimensions images.

Documents sections rearranged.

2017-03-20

V.26

John Hartfiel

Notes on Clocking section.

2017-01-27

v.25

Jan Kumann

New block diagram.

2016-12-01

v.17

Jan Kumann

Changes in the document structure, few corrections.

2016-11-18

v.14

Thorsten Trenz, Emmanuel Vassilakis

Hardware revision 02 specific changes.

2016-06-01

v.9

Antti Lukats

Initial version.

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Trenz Electronic Documentation

Versions Compared

Old Version 36

New Version 37

Key

Initial Delivery State

Control Signals

On-board LED's

Clock

Board to Board (B2B) I/Os

Power Rails

Bank Voltages

Board to Board Connectors

Absolute Maximum Ratings

Recommended Operating Conditions

Weight

Variants Currently In Production

Hardware Revision History