CompactPCI connector J2 J3 is not fittedby default on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2.
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Table_SIP_cPCI_J2J3_io
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cPCI J2 J3 interfaces
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Interfaces
I/O Signal Count
LVDS-pairs count
Connected to
VCCO bank Voltage
Notes
USB2
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1 (RX/TX)
USB2 PHY U13
-
USB2 OTG A-Device (host)
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On the header J13, there is also a optional reference clock signal from PLL clock U14 available, which can be also if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.
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Figure_SIP_10pin_jtag_uart
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10-pin JTAG/UART header
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Document change history
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small corrections
v.101
John Hartfiel
style changes
v.97
Ali Naseri
added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)