Page History
...
| Scroll Only (inline) |
|---|
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
| Scroll pdf ignore | ||||
|---|---|---|---|---|
Table of contents
|
Overview
Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
Feature Summary
- Power Management
- Reset Management
- LED Control
- FAN Control
- I2C MUX
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Description | |
|---|---|---|---|---|
| 200MHZCLK_EN | out | 30 | ||
| BUTTON | in | 77 | Reset Button | |
| CPLD_JTAG_TCK | 91 | not accessible as IO | ||
| CPLD_JTAG_TDI | 94 | not accessible as IO | ||
| CPLD_JTAG_TDO | 95 | not accessible as IO | ||
| CPLD_JTAG_TMS | 90 | not accessible as IO | ||
| DDR3_SCL | inout | 43 | I2C connected to FPGA | |
| DDR3_SDA | inout | 42 | I2C connected to FPGA | |
| DONE | in | 18 | FPGA Done | |
| EN_1V8 | out | 58 | Power Enable | |
| EN_3V3FMC | out | 60 | Power Enable | |
| EN_FMC_VADJ | out | 51 | Power Enable | |
| F1PWM | out | 98 | FAN | |
| F1SENSE | in | 99 | FAN / currently_not_used | |
| FEX_DIR | 19 | / currently_not_used | ||
| FEX0 | out | 12 | PERST from PCIe slot | |
| FEX1 | 15 | / currently_not_used | ||
| FEX10 | 4 | / currently_not_used | ||
| FEX11 | in | 10 | User LED | |
| FEX2 | 13 | / currently_not_used | ||
| FEX3 | 9 | / currently_not_used | ||
| FEX4 | 3 | / currently_not_used | ||
| FEX5 | 7 | / currently_not_used | ||
| FEX6 | 24 | / currently_not_used | ||
| FEX7 | 17 | / currently_not_used | ||
| FEX8 | 21 | / currently_not_used | ||
| FEX9 | 25 | / currently_not_used | ||
| FMC_PG_C2M | 69 | / currently_not_used | ||
| FMC_PG_M2C | 68 | / currently_not_used | ||
| FMC_PRSNT_M2C_L | 70 | / currently_not_used | ||
| FMC_SCL | 49 | I2C connected to FPGA | ||
| FMC_SDA | 48 | I2C connected to FPGA | ||
| FMC_TCK | 27 | / currently_not_used | ||
| FMC_TDI | 31 | / currently_not_used | ||
| FMC_TDO | 32 | / currently_not_used | ||
| FMC_TMS | 28 | / currently_not_used | ||
| FMC_TRST | 36 | / currently_not_used | ||
| FPGA_IIC_OE | 14 | I2C FPGA | ||
| FPGA_IIC_SCL | 1 | I2C FPGA | ||
| FPGA_IIC_SDA | 16 | I2C FPGA | ||
| LED1 | out | 76 | Status LED D1 (green) | |
| LTM_1V_IO0 | 86 | Power Good | ||
| LTM_1V_IO1 | 88 | Power Good | ||
| LTM_1V5_4V_IO0 | 85 | Power Good | ||
| LTM_1V5_4V_IO1 | 83 | Power Good | ||
| LTM_1V5_RUN | 74 | / currently_not_used | ||
| LTM_4V_RUN | 75 | / currently_not_used | ||
| LTM_SCL | 67 | I2C connected to FPGA | ||
| LTM_SDA | 66 | I2C connected to FPGA | ||
| LTM1_ALERT | 65 | / currently_not_used | ||
| LTM2_ALERT | 64 | / currently_not_used | ||
| PCIE_RSTB | in | 37 | PERST from PCIe card edge connector | |
| PG_1V8 | in | 59 | Power Good | |
| PG_3V3 | in | 61 | Power Good | |
| PG_FMC_VADJ | in | 52 | Power Good | |
| PLL_SCL | inout | 2 | I2C SI5338 | |
| PLL_SDA | inout | 8 | I2C SI5338 | |
| PROGRAM_B | out | 20 | FPGA PROG_B | |
| VID0_FMC_VADJ | out | 53 | FMC EN5365QI power selection pin | |
| VID1_FMC_VADJ | out | 54 | FMC EN5365QI power selection pin | |
| VID2_FMC_VADJ | out | 57 | FMC EN5365QI power selection pin |
...
Functional Description
JTAG
CPLD JTAG is always enabled.
Power
Power sequence on will be executed over 4 States:
...
State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to 1.8V.
Reset
PROGRAM_B is controlled by push button after power up sequencing is ready.
CLK
200MHz CLK is enabled after power up.
I2C
Connect SI5338, LTM and FMC, SODIMM I2C and internal FAN Control to FPGA I2C Bus.
FAN1
I2C Baseaddress: 0x74 (changeable with Firmware update). I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 20 MHz supported.
...
| Register Address | Name | Description |
|---|---|---|
| 0 | FAN CTRL | FAN Control register |
| 1 | FAN1 RPS | FAN1 Revolutions per second |
Button
Button is debounced and controls PROG_B signal from FPGA.
LED
LED is used as Status LED for power management and programming. Status depends on blink sequence.
| Status | Blink sequence | Comment |
|---|---|---|
| Error - Power IDLE state | ******** | Reset or Main Power Problem |
| Error - Power PS1 state | *****ooo | Periphery Power Problem (1.8V, 3.3V, FMC VADJ) |
| Error - Power PS2 state | ****oooo | DDR Bank Power Problem (1.5V) |
| Power Ready, FPGA not programmed | ***ooooo | ~0,7 Hz, duty cycle 3/8 |
| -- | **oooooo | ~0,7 Hz, duty cycle 2/8, currently not used |
| -- | *ooooooo | ~0,7 Hz, duty cycle 1/8, currently not used |
| User Mode | user defined | Power Ready, FPGA programmed, LED is accessible over FEX11 |
...
Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
- I2C for SI5338, LTM, FMC, SODIMM
- Add FAN Control over I2C
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
...
| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV02 | REV01 |
|
| ||||||||||||||||||||||
| 2017-08-06 | v.4 | REV01 | REV01 | John Hartfiel |
| ||||||||||||||||||||||
| 2017-05-29 | v.1 | --- |
|
| |||||||||||||||||||||||
| All |
|
Appx. A: Legal Notices
| Include Page | ||||
|---|---|---|---|---|
|
Overview
Content Tools