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It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
Use 3.3V or 1.8V output to enable external power supplies or power switches which are used to supply FPGA banks.
See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.
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Date | Revision | Contributors | Description | ||||||||||||||||||||||
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| v.89 | John Hartfiel |
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| 2017-11-10 | v.85 | John Hartfiel |
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| 2017-09-07 | v.84 | John Hartfiel |
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| 2017-08-31 | v.83 | Jan Kumann |
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Table 25: Document change history table.
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