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JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
|---|---|
| TMS | JM2-12 |
| TDI | JM2-10 |
| TDO | JM2-8 |
| TCK | JM2-6 |
Table 4: JTAG pins connection
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Notes :
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| Chip/Interface | IC | PS7 Peripheral | Notes |
|---|---|---|---|
| SPI Flash | S25FL127SABMFV10 | QSPI0 | 16 MByte Flash |
| I2C EEPROM | 24LC64 | I2C0 |
| 64 KByte EEPROM | |||
| RTC I2C | RV-3029 | I2C0 | |
| RTC Interrupt | RV-3029 | GPIO - MIO0 | |
| User LED | LED Green | GPIO - MIO7 |
Table 5: On board Peripherals
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Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.
| MIO Pin | Schematic | U13 Pin | Notes |
|---|---|---|---|
| MIO1 | SPI_CS | A1 | |
| MIO2 | SPI_DQ0/M0 | A2 | |
| MIO3 | SPI_DQ1/M1 | F6 | |
| MIO4 | SPI_DQ2/M2 | E4 | |
| MIO5 | SPI_DQ3/M3 | A3 | |
| MIO6 | SPI_SCK/M4 | A4 |
Table 6: Quad SPI interface MIOs and pins
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Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
| Schematic | ETH1 | ETH2 | Pullup | Notes |
|---|---|---|---|---|
| CTREF | J3-57 | J3-25 | Magnetics center tap voltage | |
| TD+ | J3-58 | J3-28 | on-board | |
| TD- | J3-56 | J3-26 | on-board | |
| RD+ | J3-52 | J3-22 | on-board | |
| RD- | J3-50 | J3-20 | on-board | |
| LED1 | J3-55 | J3-23 | on-board | |
| LED2 | J3-53 | J3-21 | on-board | |
| LED3 | J3-51 | J3-19 | on-board | |
| POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
| RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
Table 10: Ethernet PHY to Zynq SoC connections.
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The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .
| MIO Pin | Schematic | U16 Pin | Notes |
|---|---|---|---|
| MIO8 | D | 1 | |
| MIO9 | R | 4 |
Table 11: CAN Tranciever interface MIOs
| Schematic | B2B | Pull up/down | Notes |
|---|---|---|---|
| CANH | J1-2 | on-board | |
| CANL | J1-4 | on-board |
Table 12: CAN Tranciever pins
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Table 14: Module power rails.
Bank Voltages
Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | |
| 501 | VCCO_MIO1_500 | 3.3V | |
| 502 | VCCO_DDR_502 | 1.5V | |
| 13 HR | VCCO_13 | 3.3V | Supplied by the carrier board. JM1 |
| 33 HR | VCCO_33 | 3.3V | Supplied by carrier board. JM3 |
| 34 HR | VCCO_34 | 3.3V | |
| 35 HR | VCCO_35 | 3.3V | Supplied by the carrier board. JM2,JM3 |
Table 15: Zynq SoC bank voltages.
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Absolute Maximum Ratings
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
| CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
| SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. |
| DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
Table 17: Absolute Maximum Ratings..
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Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
Table 18: Recommended operating conditions.
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