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Monitoring:
SI5338 CLKs:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz, SI5338 CLK(0 and 3) are configured to 125MHz by default.
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
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Template location: ./sw_lib/sw_apps/
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zynq_fsbl
TE modified 2018.2 FSBL
Changes:
- Si5338 Configuration see fsbl_hooks.c
- Add register_map.h, si5338.c, si5338.h
zynq_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0745
Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.
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