Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.

Key Features

  • Vitis/Vivado 2021.2.1
  • PetaLinux
  • SD
  • ETH (MAC from EEPROM)
  • USB
  • I2C
  • RTC
  • FMeter
  • Modified FSBL for SI5338 programming

Revision History

DateVivadoProject BuiltAuthorsDescription
Manuela Strücker
  • new assembly variants
Manuela Strücker
  • update 2021.2
  • new assembly variants
  • added jtag2axi for test purposes
John Hartfiel
  • 2019.2 update
  • FSBL rework, SI5338 Project with Clock Builder pro
  • device tree update
  • Vitis support
  • new assembly variants
John Hartfiel
  • BUGFIX in TE0745-02-45-3EA board parts


John Hartfiel
  • Rework Board Part Files
  • New assembly versions
  • Rework BD Design
  • add init.sh scripts
John Hartfiel
  • initial release
Design Revision History

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
QSPI programmingQSPI programming is not possible in other boot modes than JTAG.
  • use JTAG boot mode for QSPI programming
  • When using the carrier board TEB0745, use the optional firmware to get into JTAG boot mode.
Known Issues



Vitis2021.2.1needed, Vivado is included into Vitis installation
SI ClockBuilder Pro---optional


Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0745-02-30-1I    30_1i_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-30-2IA   30_2i_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-35-1C    35_1c_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-2I    45_2i_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-2IA   45_2i_1gb    REV02|REV01   1GB      64MB       NA         NA         
TE0745-02-45-1C*    45_1c_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-1CA   45_1c_1gb    REV02|REV01   1GB      64MB       NA         NA         
TE0745-02-45-3EA   45_3e_1gb    REV02|REV01   1GB      64MB       NA         NA         
TE0745-02-93E11-A  45_3e_1gb    REV02         1GB      64MB       NA         NA         
TE0745-02-92I11-F  45_2i_ff_1gb REV02         1GB      64MB       NA         NA         
TE0745-02-92I11-A  45_2i_1gb    REV02         1GB      64MB       NA         NA         
TE0745-02-91C11-A  45_1c_1gb    REV02         1GB      64MB       NA         NA         
TE0745-02-81C11-A  35_1c_1gb    REV02         1GB      64MB       NA         NA         
TE0745-02-72I11-A  30_2i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-71I11-A  30_1i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-71I11-AK 30_1i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs


30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs


30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs


30_2i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs


35_1c_1gbREV02         1GB      64MB       NA         NA         


45_1c_1gbREV02         1GB      64MB       NA         NA         


45_2i_1gbREV02         1GB      64MB       NA         NA         


45_2i_1gbREV02         1GB      64MB       NA         NA         


45_2i_1gbREV02         1GB      64MB       NA         NA         


45_3e_1gbREV02         1GB      64MB       NA         NA         


45_3e_1gbREV02         1GB      64MB       NA         NA         


45_3e_1gbREV02         1GB      64MB       NA         NA         


45_2i_1gbREV02         1GB      64MB       NA         NA         


30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs


30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
without RTC
TE0745-02-S007C145_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
TE0745-02-S007C2 45_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
TE0745-02-S007C345_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
TE0745-02-S012 45_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
TE0745-02-S00830_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-S009 30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-82I31-A35_2i_1gbREV02         1GB      64MB       NA         NA         
TE0745-02-72I31-AZ30_2i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-S01345_2i_1gbREV02         1GB      64MB       NA         NA         
TE0745-02-93E31-AZ45_3e_1gbREV021GB64MB       NA         NA         
TE0745-02-S01645_3e_1gbREV021GB64MB       NA         NA         
TE0745-02-S01730_1i_1gbREV021GB64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-71I31-AZ30_1i_1gbREV021GB64MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-S01830_1i_1gbREV021GB64MBNANAless MGT
TE0745-02-S014C145_2i_1gbREV021GB64MBNAwithout PLL
TE0745-02-S014C245_2i_1gbREV021GB64MBNAwithout PLL
TE0745-02-S014C345_2i_1gbREV021GB64MBNAwithout PLL

*used as reference

Hardware Modules

Design supports following carriers:

Carrier ModelNotes

*used as reference

Hardware Carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

*used as reference

Additional Hardware


For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Design sources

Additional Sources

SI5338<project folder>\misc\PLL\Si5338_BSI5338 Project with current PLL Configuration
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux
Additional design sources





BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Prebuilt files (only on ZIP with prebult content)


Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    -------------------------TE Reference Design---------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    Select (ex.:'0' for module selection guide):
  2. Press 0 and enter to start "Module Selection Guide"
  3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also Vivado Board Part Flow

  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt

    Using Vivado GUI is the same, except file export to prebuilt folder.

  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

  8. Generate Programming Files with Vitis

    run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0745 (optional)
  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.scr and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.


Not used on this Example.


  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Note: See TRM of the Carrier, which is used.

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  4. Power On PCB

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

  2. Linux Console:

    # password default disabled with 2021.2 petalinux release
    petalinux login: root
    Password: root

    Note: Wait until Linux boot finished

  3. You can use Linux shell now.

    i2cdetect -y -r 0	(check I2C 0 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB2.0 check)
  4. Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD"
      • Script will enable SFP interface after linux booting, if file is copied on SD

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
  • Monitoring:

    • SI5338 CLKs: 

      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
        , SI5338 CLK (0 and 3) are configured to 125MHz by default.

Vivado Hardware Manager

System Design - Vivado

Block Design

*clk3 is not available on the smallest SOC (xc7z030)

Block Design

PS Interfaces

Activated interfaces:

I2C0 ResetMIO
PS Interfaces


Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks si5338_clk0_clk_p] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks clk_fpga_0]

Software Design - Vitis

For Vitis project creation, follow instructions from:



Template location: "<project folder>\sw_lib\sw_apps\"


TE modified 2021.2 FSBL


  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration


Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.


U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:


Start with petalinux-config or petalinux-config --get-hw-description


  • MAC from eeprom together with uboot and device tree settings:
  • add new flash partition for bootscr and sizing


Start with petalinux-config -c u-boot


  • MAC from eeprom together with uboot and device tree settings:
  • Boot Modes:
    • # CONFIG_ENV_IS_IN_NAND is not set

Change platform-top.h:

#include <configs/zynq-common.h>
#no changes

Device Tree

/include/ "system-conf.dtsi"

/*--------------------------- QSPI -----------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

/*-------------------------- ETH PHY ---------------------*/
&gem0 {
	phy-handle = <&phy0>;
  nvmem-cells = <&eth0_addr>;
  nvmem-cell-names = "mac-address";  
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@1 {
			compatible = "marvell,88e1510";
			device_type = "ethernet-phy";
			reg = <1>;
		} ;
	} ;

/*---------------------------- USB ----------------------*/
	usb_phy0: usb_phy@0 {
		compatible = "ulpi-phy";
		#phy-cells = <0>;
		reg = <0xe0002000 0x1000>;
		view-port = <0x0170>;

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;

/*---------------------------- I2C -----------------------*/
&i2c0 {
  rtc@6F {
		compatible = "isil,isl12022";
		reg = <0x6F>;
	eeprom: eeprom@53 {
	  compatible = "microchip,24aa025", "atmel,24c02";
	  reg = <0x53>;
    #address-cells = <1>;
    #size-cells = <1>;
    eth0_addr: eth-mac-addr@FA {
      reg = <0xFA 0x06>;
	i2cmux_SFP: i2cmux@72  {
		compatible = "nxp,pca9548";
		reg = <0x72>;

		SFP@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		SFP@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		SFP@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		SFP@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		SFP@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		SFP@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		SFP@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		SFP@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;



Start with petalinux-config -c kernel


  • for Real Time Clock ISL12020MIRZ
    • CONFIG_RTC_DRV_ISL12022=y


Start with petalinux-config -c rootfs


  • For web server app:
    • CONFIG_busybox-httpd=y
  • For additional test tools only:
    • CONFIG_i2c-tools=y
    • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)


See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"


Script App to load init.sh from SD Card if available.


Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software


File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

DateDocument Revision



  • new assembly variants
2023-02-08v.14Manuela Strücker
  • Release 2021.2
  • new assembly variants
  • added jtag2axi for test purposes
2020-03-30v.13John Hartfiel
  • Release 2019.2
2019-09-18v.12John Hartfiel
  • bugfix for TE0745-02-45-3EA
2018-12-19v.11John Hartfiel
  • documentation notes


v.10John Hartfiel
  • update 2018.2
  • documentation style update


v.7John Hartfiel
  • Typo correction
2018-02-09v.6John Hartfiel
  • Release 2017.2
2017-09-11v.1John Hartfiel
  • Initial release
Document change history.

Legal Notices

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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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