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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
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Overview
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Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.
Key Features
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- PetaLinux
- SD
- ETH (use EEPROM MAC)
- USB
- I2C
- RTC
- VIO PHY LED
- FSBL for EEPROM MAC and CPLD access
- Special FSBL for QSPI Programming
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Revision History
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te0720-test_board-vivado_2018.2-build_03_20180823185142.zip
te0720-test_board_noprebuilt-vivado_2018.2-build_03_20180823185158.zip
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- DDR setup bugfix for l1if only
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- 2018.2 update
- Boart Part Files rework
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- add assembly variant
- script update
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- no design changes
- set EEPROM MAC with FSBL+u-boot
- FSBL for QSPI Programming
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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1GB
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Design supports following carriers:
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...
- See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
- Used as reference carrier.
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...
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- See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
- No SD Slot available, pins goes to Pin Header
- For TEBA0841 REV01, please contact TE support
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Table of contents |
Overview
Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.
Refer to http://trenz.org/te0712-info for the current online version of this manual and other available documentation.
Key Features
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- Vivado 2018.3
- PetaLinux
- SD
- ETH (use EEPROM MAC)
- USB
- I2C
- RTC
- VIO PHY LED
- FSBL for EEPROM MAC and CPLD access
- Special FSBL for QSPI Programming
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Revision History
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Date | Vivado | Project Built | Authors | Description |
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2019-02-21 | 2018.3 | TE0720-test_board-vivado_2018.3-build_01_20190221125123.zip TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190221125133.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- some additional Linux features
| 2018-08-23 | 2018.2 | te0720-test_board-vivado_2018.2-build_03_20180823185142.zip te0720-test_board_noprebuilt-vivado_2018.2-build_03_20180823185158.zip | John Hartfiel | - DDR setup bugfix for l1if only
| 2018-08-13 | 2018.2 | te0720-test_board-vivado_2018.2-build_02_20180810162024.zip te0720-test_board_noprebuilt-vivado_2018.2-build_02_20180810162040.zip | John Hartfiel | - 2018.2 update
- Boart Part Files rework
| 2018-04-26 | 2017.4 | te0720-test_board-vivado_2017.4-build_07_20180426144351.zip te0720-test_board_noprebuilt-vivado_2017.4-build_07_20180426144405.zip | John Hartfiel | | 2018-03-12 | 2017.4 | te0720-test_board_noprebuilt-vivado_2017.4-build_06_20180312152408.zip te0720-test_board-vivado_2017.4-build_06_20180312152419.zip | John Hartfiel | - add assembly variant
- script update
| 2018-01-09 | 2017.4 | te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip te0720-test_board-vivado_2017.4-build_02_20180109121300.zip | John Hartfiel | - no design changes
- set EEPROM MAC with FSBL+u-boot
- FSBL for QSPI Programming
| 2017-11-27 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip te0720-test_board-vivado_2017.2-build_05_20171127153006.zip | John Hartfiel | - remove duplicated content
| 2017-11-20 | 2017.2 | te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip | John Hartfiel | |
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Release Notes and Know Issues
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- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vivado | 2018.3 | needed | SDK | 2018.3 | needed | PetaLinux | 2018.3 | needed |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0720-03-2IF | 2if_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | NA | TE0720-03-2IFC3 | 2if_1gb | REV03|REV02 | 1GB | 32MB | 4GB | 2.5 mm connectors | NA | TE0720-03-2IFC8 | 2if_1gb | REV03|REV02 | 1GB | 32MB | 32GB | NA | NA | TE0720-03-1QF | 1qf_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | NA | TE0720-03-1CF | 1cf_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | NA | TE0720-03-1CFA | 1cf_1gb | REV03|REV02 | 1GB | 32MB | 8GB | NA | NA | TE0720-03-2EF | 2ef_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | NA | TE0720-03-1CR | 1cr_256mb | REV03|REV02 | 256MB | 32MB | NA | NA | NA | TE0720-03-L1IF | l1if_512mb | REV03|REV02 | 512MB | 32MB | 4GB | NA | LP DDR3 | TE0720-03-14S-1C | 14s_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | NA | TE0720-03-1QFA | 1qf_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | Micron Flash | TE0720-03-2IFA | 2if_1gb | REV03|REV02 | 1GB | 32MB | 4GB | NA | Micron Flash | TE0720-03-1QFL | 1qf_1gb | REV03|REV02 | 1GB | 32MB | 4GB | 2.5 mm connectors | NA |
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Design supports following carriers:
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Carrier Model | Notes |
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TE0701 | | TE0703 | - See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
- Used as reference carrier.
| TE0705 | | TE0706 | | TEBA0841 | - See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
- No SD Slot available, pins goes to Pin Header
- For TEBA0841 REV01, please contact TE support
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Additional HW Requirements:
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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Content
For general structure and of the reference design, see Project Delivery
Design Sources
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
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Type | Location | Notes |
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init.sh | <design name>/sd/ | Additional Initialization Script for Linux |
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Prebuilt
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- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
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Additional HW Requirements:
...
Content
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For general structure and of the reference design, see Project Delivery
Design Sources
...
Additional Sources
...
Prebuilt
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<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
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File
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File-Extension
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Description
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| BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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- Important set new Vivado version link on every Design update of new vivado version!
- Set Link to download folder (Remove ../de/.. ../en/.. from url) for example
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Reference Design is available on:
Design Flow
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Basic Design Steps
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image RemovedImage Added - Press 0 and enter for minimum setupto start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Programming
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Note: - Programming and Startup procedure
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Note |
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
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- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0720" possible - Copy image.ub on SD-Card
- Insert SD-Card
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Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
--> |
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB: insert USB device
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
PHY LED:
Image Removed
System Design - Vivado
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Block Design
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SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 68616214
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB: insert USB device
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder
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System Design - Vivado
Block Design
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PS Interfaces
Type | Note |
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DDR | --- |
QSPI | MIO |
ETH0 | MIO |
USB0 | MIO |
SD0 | MIO |
SD1 | MIO |
UART0 | MIO |
UART1 | MIO |
I2C0 | MIO |
I2C1 | EMIO |
GPIO | MIO |
TTC0..1 | EMIO |
WDT | EMIO |
Constrains
Basic module constrains
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language | ruby |
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title | _i_bitgen_common.xdc |
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#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design |
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#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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title | _i_TE0720-SC.xdc |
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#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
SDK Projects
Application
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---------------------------------------------------------- FPGA Example todo.. ---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0720
Hello World App in Endless loop.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
- CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenv dfu_alt_info " \
"image.ub ram $netstart 0x1e00000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
#define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0 |
Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen_common.xdc |
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#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design |
Code Block |
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language | ruby |
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title | _i_common.xdc |
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|
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
Code Block |
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language | ruby |
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title | _i_TE0720-SC.xdc |
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|
#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Software Design - SDK/HSI
HTML |
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<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
SDK Projects
Application
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2018.2 FSBL
Functions:
- Read EEPROM MAC Address and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- Read CPLD Firmware and SoC Type
- CPLD Interface
- Configure Marvell PHY
Changes:
- Add te_fsbl_config.h, te_fsbl_hooks.h te_fsbl_hooks.c, and includ into fsbl_hooks.c
zynq_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0720
Hello World App in Endless loop.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
HTML |
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<!--
optional chapter
Add "No changes." or "Activate: and add List"
--> |
For PetaLinux installation and project creation, follow instructions from:
Config
- Subsystem Auto Hardware Settings:Serial Settings: ps7_uart_0
U-Boot
Code Block |
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenvthor_mmc=run dfu_altmmc_info "&& \
thordown 0 "image.ub ram $netstart 0x1e00000mmc 0\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
#define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
/*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQ_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN "set dfu_alt_info " \
1
#define CONFIG_SYS_I2C_EEPROM_ADDR "${kernel_image} fat 0 1\\\\;" \
0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
1024 /*Required forBytes uartless designs */
#ifndef#define CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
/*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQ_EEPROMSYS_I2C_MUX_ADDR 0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_ADDR_LENSEL 10x4
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
#define CONFIG_SYS_I2C_MUX_ADDR 0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_SELPREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"
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Device Tree
Code Block |
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/include/ "system-conf.dtsi"
/ {
};
/* default */
/* QSPI PHY */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible 0x4
#endif
#define CONFIG_PREBOOT= "jedec,spi-nor";
"echo U-BOOT for petalinux;echo importingreg env= from<0x0>;
FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00#address-cells == 0xCAFEBABE<1>;
then echo Found valid magic; env import #size-tcells 0xFFFFFC04;= fi<1>;setenv
preboot; echo; dhcp"
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Device Tree
Code Block |
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/include/ "system-conf.dtsi"
/ { };
};
/* default */
/* QSPIETH PHY */
&qspigem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0phy0: flash@0phy@0 {
compatible = "jedecmarvell,spi-nor88e1510";
reg device_type = <0x0>"ethernet-phy";
#address-cellsreg = <1><0>;
#size-cells = <1> };
};
};
/* ETHUSB PHY */
&gem0 /{
phy-handle = <&phy0>;
usb_phy0: usb_phy@0 {
compatible mdio {= "ulpi-phy";
#address-cells//compatible = <1>"usb-nop-xceiv";
#size#phy-cells = <0>;
phy0: phy@0 {reg = <0xe0002000 0x1000>;
compatibleview-port = "marvell,88e1510"<0x0170>;
device_type = "ethernetdrv-phy"vbus;
};
};
&usb0 {
reg dr_mode = <0>"host";
//dr_mode = "peripheral";
};
usb-phy = }<&usb_phy0>;
};
/* I2C need USBI2C1 PHY */
/{
usb_phy0: usb_phy@0 {connected to te0720 system controller ip */
&i2c1 {
iexp@20 { compatible = "ulpi-phy";
//compatible GPIO = "usb-nop-xceiv";in CPLD
#phy#gpio-cells = <0><2>;
regcompatible = <0xe0002000 0x1000>"ti,pcf8574";
view-portreg = <0x0170><0x20>;
drvgpio-vbuscontroller;
};
};
&usb0 {
iexp@21 { // GPIO in CPLD
dr_mode #gpio-cells = "host"<2>;
//dr_modecompatible = "peripheralti,pcf8574";
usb-phy reg = <&usb_phy0>;
};
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {<0x21>;
gpio-controller;
};
iexp@20rtc@6F { // GPIOReal inTime CPLDClock
#gpio-cellscompatible = <2>"isl12022";
compatible = "ti,pcf8574";
reg = reg = <0x20>;
gpio-controller;
};
iexp@21 { // GPIO in CPLD
#gpio-cells = <2>;
compatible = "ti,pcf8574";
reg = <0x21>;
gpio-controller;
};
rtc@6F { // Real Time Clock
compatible = "isl12022";
reg = <0x6F>;
};
}; |
Kernel
Activate:
Rootfs
Activate:
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
HTML |
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<!--
Add Description for other Software, for example SI CLK Builder ...
--> |
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_RTC_DRV_ISL12022=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Page properties |
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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anchor | Table_dch |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
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Date | Document Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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| Page info |
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| current-version |
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| current-version |
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prefix | v. |
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| Page info |
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| modified-user |
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| modified-user |
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| - 2018.3 release finished (include design reworks)
| 2018-08-30 | v.25 | John Hartfiel | - update documentation PS configuration
| 2018-08-23 |
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...
| v.24 | John Hartfiel | | 2018-08-13 |
|
...
| v.23 | John Hartfiel | | 2018-04-26 |
|
...
| v.22 | John Hartfiel | | 2018-02-20 | v.20 | John Hartfiel | - small documentation update
| 2018-01-09 | v.16 | John Hartfiel | - Release 2017.4
- Documentation update
| 2017-11-27 | v.14 | John Hartfiel | - Typo correction
- Design Files update
| 2017-11-22 | v.12 | John Hartfiel | | 2017-11-22 | v.11 | John Hartfiel | | 2017-11-20 | v.1 | | | -- | All | Page info |
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| modified-users |
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| -- |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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...