...
| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General PL I/O to B2B connectors information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
|---|
| Bank 1A |
Bank 1BBank 2Bank Bank 56Bank 8 |
...
JTAG access to the TExxxx SoM through B2B connector JMX.
...
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
| 5 | 3.3V | JTAG interface | | Bank 2 | J1 | 4 | 3.3V | D2...5 | | Bank 5 | J2 | 9 | 3.3V | D6...14 | | J1 | 2 | 3.3V | D0...1 | | Bank 8 | J2 | 1 | 3.3V | RESET |
|
JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | Pin Header Connector |
|---|
| TMS | J4-6 | | TDI | J4-5 | | TDO | J4-4 | | TCK | J4-3 | | JTAG_EN | J4-2 |
|
FPGA I/O Banks
| Page properties |
|---|
|
you must fill the table below with group of MIOs which are connected to a specific components |
...
JTAG Signal
...
B2B Connector
...
MIO Pins
| Page properties |
|---|
|
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: |
| MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
in the Schematic.
Example:
| MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
| Scroll Title |
|---|
| anchor | Table_OBP_IOs |
|---|
| title | FPGA I/O Banks |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
|---|
| Bank 1A | J1 | 7 | 3.3V | AIN0...6 | | Bank 1B | J4 | 5 | 3.3V | JTAG interface | | Bank 2 | J1 | 4 | 3.3V | D2...5 | | Bank 5 | J2 | 9 | 3.3V | D6...14 | | J1 | 2 | 3.3V | D0...1 | | Bank 8 | J2 | 1 | 3.3V | RESET |
|
| Scroll Title |
|---|
| anchor | Table_OBP_MIOs |
|---|
| title | MIOs pins |
|---|
|
| Scroll Table Layout |
|---|
|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| MIO Pin | Connected to | B2B | Notes
On-board Peripherals
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...