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Template Revision 2.6

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
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        Scroll Table Layout
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TEI0015 is an commercial-grade, low cost and small size module integrated with Intel® MAX 10.  Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Intel® MAX 10 Commercial [10M08SAU169C8G]
    • Package: 169-UBGA
    • Speed Grade: C8 (Slowest)
    • Temperature: 0°C ~ 85°C
  • SDRAM Memory up to 64Mb, 166MHz
  • Dual High Speed USB to Multipurpose UART/FIFO IC
  • Quad SPI Flash, 64Mb
  • EEPROM Memory, 4Kb
  • 8x User LED 

  • USB port

  • 18 Bit Analog to Digital Converter

  • 2x SMA Female Connector

  • Power Supply:

    • 5V

  • Others:

    • Dimension: 86m x 25m

    • Instrumentation Amplifier

    • Voltage Feedback Amplifier

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titleTEI0015 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titleTEI0015 main components


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  1. SMA Connector, J5...6
  2. Instrumentation Amplifier, U12- U14
  3. Series Voltage Reference, U8
  4. Analog to Digital Convertor, U15- U6
  5. Voltage Regulator, U10- U13- U16
  6. Buck Switching Regulator, U11- U4
  7. Intel® MAX 10, U1
  8. SDRAM Memory, U2
  9. SPI Flash Memory, U5
  10. USP to UART convertor, U3
  11. User LEDs, D2...9
  12. 4Kb EEPROM, U9
  13. Switch, S1...2
  14. USB port, J9
  15. Pin Holder (Not assembled), J1...4

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


I2C Configuration EEPROM

Programmed


SDRAMNot Programmed



Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Reset process must be done by pressing push button S1.

Scroll Title
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titleReset process.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2connected to nCONFIG


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

I/Os on Pin Headers and Connectors

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titleGeneral I/Os to Pin Headers and connectors information

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FPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Bank 1AJ173.3VAIN0...6
Bank 1BJ453.3VJTAG interface
Bank 2J143.3VDIO2...5
Bank 5J293.3VDIO6...14
J123.3VDIO0...1
Bank 8J213.3VRESET


FPGA I/O Banks

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
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titleFPGA I/O Banks

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FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 241x14 Pin header, J1D2...5

5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV

112MHz Oscillator, U7CLK12M

2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 88User Red LEDs, D2...9LED0...7

6SPI Flash, U5F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn

1Red LED, D10CONF_DONE

6FTDI JTAG/UART Adapter, U3BDBUS0...5

1Push Button, S2USER_BTN


JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4.

Scroll Title
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titleJTAG pins connection

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JTAG Signal

Pin Header Connector

TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3

JTAG_ENJ4-2


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
















Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


Scroll Title
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titleQuad SPI interface MIOs and pins

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MIO PinSchematicU?? PinNotes


























RTC

Scroll Title
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titleI2C interface MIOs and pins

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MIO PinSchematicU? PinNotes










Scroll Title
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titleI2C Address for RTC

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MIO PinI2C AddressDesignatorNotes






EEPROM

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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MIO PinSchematicU?? PinNotes










Scroll Title
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titleI2C address for EEPROM

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MIO PinI2C AddressDesignatorNotes





LEDs

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titleOn-board LEDs

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SchematicColorConnected toActive LevelNote
















DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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BankSignal NameETH1ETH2Signal Description







































































CAN Transceiver

Scroll Title
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titleCAN Tranciever interface MIOs

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BankSchematicU?? PinNotes

D-Tx
Driver Input

R-Rx
Reciever Output



Clock Sources

Scroll Title
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titleOsillators

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DesignatorDescriptionFrequencyNote


MHz


MHz


KHz





Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
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titlePower Distribution


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Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


Scroll Ignore

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Voltage Monitor Circuit

Scroll Title
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titleVoltage Monitor Circuit


Scroll Ignore

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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

    Operating Temperature: -??°C ~ ??°C
    Current Rating: ??A per ContactNumber of Positions: ??
    Number of Rows: ??

Technical Specifications

Absolute Maximum Ratings

Scroll Title
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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit




V




V




V




V




V




V




V




V











Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

  • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ? mm.

PCB thickness: ?? mm.

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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titlePhysical Dimension


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scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

if not available, set.


Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

List of online PCN ...Link

Scroll Title
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titleHardware Revision History

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DateRevisionChanges
-





Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse


Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • change list

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices