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| Scroll Title |
|---|
| anchor | Table_OBP_QSPI |
|---|
| title | Quad SPI Flash memory interface |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Signal Schematic Name | Connected to | Notes |
|---|
| F_CS | FPGA bank 8, pin B3 | chip select | | F_CLK | FPGA bank 8, pin A3 | clock | | F_DI | FPGA bank 8, pin A2 | data in / out | | nSTATUS | FPGA bank 8, pin C4 | data in / out, configuration dual-purpose pin of FPGA | | DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA | | F_DO | FPGA bank 8, pin B2 | data in / out |
|
EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Scroll Title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Connected to | Notes |
|---|
EECS | FTDI U3, Pin EECS |
| | EECLK | FTDI U3, Pin EECLK |
| | EEDATA | FTDI U3, Pin EEDATA |
|
|
LEDs
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROMLED |
|---|
| title | I2C address for EEPROMOn-board LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
LEDs
...
| anchor | Table_OBP_LED |
|---|
| title | On-board LEDs |
|---|
...
DDR3 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
...
| anchor | Table_OBP_ETH |
|---|
| title | Ethernet PHY to Zynq SoC connections |
|---|
| Connected to | Active Level | Note |
|---|
| D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V Power Rail | Active High | After power on it will be on |
|
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CAN Transceiver
| Scroll Title |
|---|
| anchor | Table_OBP_CAN |
|---|
| title | CAN Tranciever interface MIOs |
|---|
|
| Scroll Table Layout |
|---|
|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| Bank | Schematic | U?? Pin | Notes |
|---|
D-Tx | Driver Input | R-Rx | Reciever Output
Clock Sources
| Scroll Title |
|---|
| anchor | Table_OBP_CLK |
|---|
| title | Osillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Clock Source | Schematic Name | Frequency | Note |
|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
|
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