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Schematic net nameDefault functionDirectionSC pinFPGA pinDescription
XCLKETH PHY Clock to FPGAto FPGAK1K19 
X1I2C Clock from FPGAfrom FPGAF1L16SCL from EMIO I2Cx
X7I2C Data from FPGAfrom FPGAM1N22SDA from EMIO I2Cx
X5I2C Data to FPGAto FPGAJ1P22SDA to EMIO I2Cx
X2ETH PHY LED1LED0to FPGAC2M15 
X4ETH PHY LED2to FPGAD1P16 
X3InterruptETH PHY LED1to FPGAB1N15RTC, MEMS Interrupt or PHY LED3LED1
X0  

--not used on TE0720-02
PUDC   


K16normally not used tied to fixed level by SC

 

 



It is recommended to use Vivado IP Core available for 2014.2 and later versions.

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Pin/FunctionUsed as/Mapped to Notes
ETH PHY LED0XIO to FPGA 
ETH PHY LED1XIO to FPGA 
ETH PHY LED2Not used XIO to FPGA
ETH PHY CONFIGTied logic lowPHY Address set to 0
ETH CLK125MHzPass through FPGA B34 SRCC pin 
ETH Clock EnableTied logic high 
ETH PHY ResetInternal RESET 
MIO7LED1 
MEMS/RTC I2CXIO to FPGA 
RTC Interrupt-  
MEMS Interrupt 1 -  
MEMS Interrupt 2- 
eMMC ResetInternal RESET 
USB PHY ResetInternal RESET 
FPGA PUDCTied logic low  
FPGA PROG_BTied logic high 
Zynq Cascaded JTAG Enabled (pulled low)  
Zynq boot mode SPI or SD, depending on bootmode pin  
Zynq SRSTTied logic high  
Zynq PORInternal POR/Reset 
PLLNot used 
LED2System Status LED 
LED1MIO7 
NOSEQ InputNOSEQ at power, LED out after boot 
Power Good 1.5V  

Power Good VTT  

MODE Input  


I2C AddressFunction 
0x20Status reg 1 
0x21Status reg 2 

LED Control Status

The TE0720 on-board LED devices can be remapped to different functions.

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AddrR/WRegister nameDescripion
0RO 

1RO  

2ROID1Identifier Register 1
3ROID2Identifier Register 2
4ROID3Identifier Register 3
5RWCR1Control Register 1: LED's
6RWCR2Control Register 2; XIO Control
7RWCR3Control Register 3; Reset, Interrupt
8ROSR1Status Register
9ROMAChiHighest bytes of primary MAC Address
0xAROMACmiMiddle bytes of primary MAC Address
0xBROMACloLowest bytes of primary MAC Address
0xCCR4 
reserved do not use
0xDRWMMD_CRMMD Control Register
0xERWMMD_ADMMD Address/Data
0xF- 
reserved do no use
other- 
reserved do not use

 


Register CR1

BitDescription
15:12-
11:8Noseq MUX
7:4LED2 MUX
3:0LED1 MUX


ValueLED1LED2NOSEQ 
DefaultMIO7Mode BlinkPHY_LED0 
0001PHY_LED0PHY_LED0PHY_LED0 
0010PHY_LED1PHY_LED1PHY_LED1 
0011PHY_LED2PHY_LED2PHY_LED2 
0100MIO7MIO7MIO7 
0101RTC_INTRTC_INTRTC_INT 
0110OFFOFFOFF 
0111ONONON 
1000MIO14/MIO15MIO14/MIO15 
REV 05, UART activity
1001MIO14MIO15 
REV 05
1010   


REV 05

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Register CR2

BitDescription
15:12XCLK select
11:8XIO6 select
7:4XIO5 select
3:0XIO4 select

 


Signal XIO4

XIO4 selectSignal out value
"0001"MIO7
"0010"SHA_IO
"0011"MAC_IO
"0110"'Z' (Configured as input)
all othersPHY_LED0

 


Signal XIO5

XIO5 selectSignal out value
"0101"RTC_INT
"0110"'Z' (Configured as input)
all othersPHY_LED1

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Signal XIO6

XIO6 selectSignal out value
"0110"'Z' (Configured as input)
"0111"INTR
all othersPHY_LED2

 


Signal XCLK

XCLK SelectSignal out value
"0001"RTC_INT
"0010"Internal Oscillator Out ~24.18 MHz
all others125 MHz

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Signal SHA_IO

XIO4 selectSignal out value
"0010"XIO5
all others'Z' (Configured as input)

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Signal MAC_IO

XIO4 SelectSignal out value
"0011"XIO5
all othersConnected to internal MAC read block

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System Controller version 0.02 does not support extended address space - registers 0xD and 0xE are read-write accessible but do not have any function. In feature revision extended address will be used to control SC PLL and other features.

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Interrupt can be selected instead of PHY_LED2 on XIO6 pin, by setting CR2 bits 11 downto 8 to "0111"

 

 



Overview: On-board LEDs

There are 3 on-board LEDs, with two of them connected to the System Management Controller and one to the Zynq PL (Done pin).

NameColorConnected to:Default mapping:
LED1GreenSCPL MIO[7]
LED2RedSCSystem Controller Status LED
LED3GreenZynq PLFPGA Done - active low

LED1 GREEN

Is mapped to MIO7 after power up. After the Zynq PS has booted it can change the mapping of this LED. If SC can not enable power to the Zynq then this LED will remain under SC control. It is available to the user only after the power supplies have stabilized and the POR reset to the Zynq is released.

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Note
This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module.

LED Status Codes

#GLED1RLED2GLED3StatusDescription
1OFFOFFONFatal power errorThis combination after power up is only possible in no sequencing compatibility mode were 3.3Vout is supplied externally. The 1.0V and 1.8V DC-DC supplies are forced on (NOSEQ=1), and the SC is not able to start (3.3Vin below 2.1V). This should never happen if the external power supplies are OK.
2OFFONOFFVIN missing (or EN1 low)3.3Vin is present, but the DC-DC supplies are not powered or 3.3Vin is below 3.05V. If the LEDs stay on in this state then 3.3Vout is not turned on, and the Zynq is kept in the POR state.
3OFF1/2 Blink Fast 4 HzONOKBoot mode selected is SPI Flash. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded.
4OFF1/2 Blink Slow 1 HzONOKBoot mode selected is SD Card. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded.
5MIO7 or user functionBlink or user functionOFFOKLED3 goes off when the FPGA is configured. NOTE: The FPGA design can control this LED too using STARTUPE2, so it may remain ON or be flashing when the FPGA is configured.
6ONSlow blink 0.5Hz, 1/8 on, 7/8 offOFFPowerdownEN1 input to the module is low. If sequencing is enabled in this mode, then all power supplies on the module are OFF.
7ONSlow blink 0.5Hz, 1/8 on, 7/8 offON
 

EN1 input to the module is low. Sequencing is disabled module is in reset state.
8ONONONResetPowered, RESIN input is active low or Bank B34 Supply Voltage is missing.

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If green LED3 does not light up at least for short time at power then there is major problem with power supplies, FPGA core and aux voltages may be missing.

 

 

 





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Overview

Firmware for PCB CPLD with designator U19.  CPLD Device in Chain: LCMX02-1200HC

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