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Excerpt
  • Vivado 2018.3
  • UART
  • I2C
  • FMeter
  • Modified FSBL for DDR Less Zynq
  • Modified FSBL for DDR Less Zynq + small app with LED+Sensor access
  • Special FSBL for QSPI programming

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DateVivadoProject BuiltAuthorsDescription
2019-05-222018.3TE0722-test_board-vivado_2018.3-build_05_20190522113216.zip
TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190522113228.zip		John Hartfiel
  • split FSBL into 2 templates, one with and one without  Sensor+LED access example app
2019-05-142018.3TE0722-test_board-vivado_2018.3-build_05_20190510163659.zip
TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190510163900.zip		John Hartfiel
  • TE Script update
  • rework of the FSBLs
    • DDR LESS, Device ID, Sensor+LED access
  • VIO for RGB access
2018-08-142018.2TE0722-test_board-vivado_2018.2-build_02_20180815123557.zip
TE0722-test_board_noprebuilt-vivado_2018.2-build_02_20180815123610.zip		John Hartfiel
  • initial release


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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints		Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI


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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"

    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: Vivado TCL: TE::sw_run_sdk
      Note: Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)

      See SDK Projects

      Info

      TE0722  is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design


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  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp zynq_fsbl_app
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

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  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Output:
    1. Default output appears only 10 time. Reboot device: force ResN Pin to GND for short time, location see: TE0722 Getting Started
      Image RemovedStarted
      Image Addedalternately: comment define #define ENABLE_TE_HOOKS_BH on te_fsbl_hooks.h to disable Sensor and LED access example and regenerate FSBL and Boot.bin again

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequ:...

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FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Source location: \sw_lib\sw_apps

...

Boot.bin.

Source location: \sw_lib\sw_apps

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID
    • Disable Memory initialisation on main.c

zynq_fsbl_app

TE modified 2018.3 FSBL

General:

...

  • Add Files: all TE Files start with te_*
    • Example app for LED access over MIO and sensor access over I2C

zynq_fsbl_flash

TE modified 2018.3 FSBL

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  • separate template for FSBL with App included
2019-05-14v.6John Hartfiel
  • 2018.3 release
2018-08-15v.5John Hartfiel
  • 2018.2 release
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