Page properties |
---|
|
Template Revision 2.6 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
HTML |
---|
<!--
Template Revision 1.0
Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
--> |
Scroll Only (inline) |
---|
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Scroll pdf ignore |
---|
Table of contents |
Overview
HTML |
---|
<!--
General Design description
--> |
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.
Key Features
HTML |
---|
<!--
Add Basic Key Features of the design (should be tested)
--> |
Excerpt |
---|
- QSPI
- SDK
- Custom Carrier (minimum PS Design with available module components only)
- Special FSBL for QSPI Programming
|
Revision History
HTML |
---|
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
--> |
...
...
- additional notes for FSBL generated with Win SDK
- changed *.bif
...
...
...
Release Notes and Know Issues
HTML |
---|
<!--
- add known Design issues and general Notes for the current revision
--> |
...
Requirements
Software
HTML |
---|
<!--
Add needed external Software
--> |
...
Hardware
HTML |
---|
<!--
Hardware Support
--> |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
...
Additional HW Requirements:
...
Content
HTML |
---|
<!--
Remove unused content
--> |
For general structure and of the reference design, see Project Delivery
Design Sources
...
tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
Page properties |
---|
|
Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
|
Scroll pdf ignore |
---|
Table of contents |
Overview
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.
Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
---|
|
Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
---|
- Vivado 2018.3
- QSPI
- SDK
- Custom Carrier (minimum PS Design with available module components only)
- Modified FSBL (some additional outputs only)
- Special FSBL for QSPI Programming
|
Revision History
Page properties |
---|
|
Notes : - add every update file on the download
- add design changes on description
|
Scroll Title |
---|
anchor | Table_DRH |
---|
title | Design Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Vivado | Project Built | Authors | Description |
---|
2019-05022 | 2018.3 | TE0807-test_board_noprebuilt-vivado_2018.3-build_05_20190522132408.zip TE0807-test_board-vivado_2018.3-build_05_20190522132356.zip | John Hartfiel | - custom FSBL
- Note: Prebuilt for ES2 version not included
| 2019-02-08 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_04_20190207111539.zip TE0807-test_board-vivado_2018.2-build_04_20190207111524.zip | John Hartfiel | | 2018-09-04 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_03_20180904121458.zip TE0807-test_board-vivado_2018.2-build_03_20180904121522.zip | John Hartfiel | - additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-01-18 | 2017.4 | TE0807-test_board_noprebuilt-vivado_2017.4-build_05_20180118152119.zip TE0807-test_board-vivado_2017.4-build_05_20180118152104.zip | John Hartfiel | | | 2017.2 | TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip | John Hartfiel | |
|
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Issues | Description | Workaround | To be fixed version |
---|
No known issues | --- | --- | --- |
|
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Software | Version | Note |
---|
Vivado | 2018.3 | needed | SDK | 2018.3 | needed |
|
Hardware
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title |
---|
anchor | Table_HWM |
---|
title | Hardware Modules |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0807-01-07EV-ES | es2_2gb | REV01 | 2GB | 64GB | NA | NA | Slower DDR Speed | TE0807-02-07EV-1E | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | NA | TE0807-02-07EV-1EK | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | with heat sink |
|
Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Scroll Title |
---|
anchor | Table_HWC |
---|
title | Hardware Carrier |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Carrier Model | Notes |
---|
Custom PCB | use simple Board Part files, if MIO connected is different to TEBF0808 | TEBF0808 | Used as reference carrier. | TEBT0808-01 | Change UART0 to UART1 (MIO68...69) and regenerate design |
|
Additional HW Requirements:
Scroll Title |
---|
anchor | Table_AHW |
---|
title | Additional Hardware |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Additional Hardware | Notes |
---|
--- | --- |
|
Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Scroll Title |
---|
anchor | Table_DS |
---|
title | Design sources |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Location | Notes |
---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
|
Additional Sources
Scroll Title |
---|
anchor | Table_ADS |
---|
title | Additional design sources |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Type | Location | Notes |
---|
--- | --- | --- |
|
Prebuilt
Page properties |
---|
|
Notes : - prebuilt files
- Template Table:
Scroll Title |
---|
anchor | Table_PF |
---|
title | Prebuilt files |
---|
| Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
File | File-Extension | Description |
---|
BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
|
|
Scroll Title |
---|
anchor | Table_PF |
---|
title | Prebuilt files (only on ZIP with prebult content) |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
Additional Sources
...
Prebuilt
HTML |
---|
<!--
<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
</table>
-->
File | File-Extension | Description |
---|
BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Page properties |
---|
|
- Important set new Vivado version link on every Design update of new vivado version!
- Set Link to download folder (Remove ../de/.. ../en/.. from url) for example
|
HTML |
---|
<!--
Add correct path/en_Electronic/TE080320171/Starterkit
--> |
Reference Design is available on:
Design Flow
Page properties |
---|
|
Notes :
|
HTML |
---|
<!--
Basic Design Steps
Add/ Remove project specific
--> |
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image RemovedImage Added - Press 0 and enter for minimum setupto start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
(follow instruction of the product selection guide), settings file will be configured automatically during this process
- S(optional for manual changes)elect Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
Launch
Programming
Page properties |
---|
|
Note: - Programming and Startup procedure
|
HTML |
---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
Note |
---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
...
...
- Connect
...
- JTAG
...
- and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with SDK Debugger into device, see:
Usage
QSPI Boot:
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
Debugging:
System Design - Vivado
Block Design
Scroll Title |
---|
anchor | Figure_BD |
---|
title | Block Design |
---|
|
Image Added |
PS Interfaces
Activated interfaces:
Scroll Title |
---|
anchor | Table_PSI |
---|
title | PS Interfaces |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with SDK Debugger into device, see:
Usage
QSPI Boot:
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
Debugging:
System Design - Vivado
HTML |
---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
Block Design
Image Removed
PS Interfaces
...
Type | Note |
---|
DDR |
| QSPI | MIO | UART0 | MIO, please select other one, if you have connected uart to second controller or other MIO | SWDT0..1 |
| TTC0..3 |
|
|
Constrains
Basic module constrains
...
Software Design - SDK/HSI
HTML |
---|
<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
SDK Projects
Application
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
Xilinx default FSBL
zynqmp_fsbl_flash
TE modified 2017.4 FSBL
For SDK project creation, follow instructions from:
SDK Projects
Application
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
...
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
Page properties |
---|
|
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
HTML |
---|
<!--
Add Description for other Software, for example SI CLK Builder ...
--> |
No additional software is needed.
...
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties |
---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
HTML |
---|
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
--> |
Date | Document Revision | Authors | Description |
---|
Page info |
---|
| modified-date |
---|
| modified-date |
---|
dateFormat | yyyy-MM-dd |
---|
|
| Page info |
---|
| current-version |
---|
| current-version |
---|
prefix | v. |
---|
|
| Page info |
---|
| modified-user |
---|
| modified-user |
---|
|
| |
2019-02-07 | v.9 | John Hartfiel | |
Sept 2018 | v.7 | John Hartfiel | |
2018-02-08 | v.5 | John Hartfiel | |
2017-11-14 | v.3 | John Hartfiel | |
-- | Allall | Page info |
---|
| modified-users |
---|
| modified-users |
---|
|
| -- |
Legal Notices
Include Page |
---|
| IN:Legal Notices |
---|
| IN:Legal Notices |
---|
|
...