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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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title | Known Issues |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vivado | 2018 |
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Hardware
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Notes : - list of software which was used to generate the design
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Design specific constrain
Not needed.
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
SDK Projects
Application
Not needed.
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
SDK Projects
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2018.3 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2018.3 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2018.3 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 2018.3 FSBL
General:
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Date | Document Revision | Authors | Description |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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infoType | Modified by |
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type | Flat |
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| - small document style update
| 2019-05-07 | v.22 | John Hartfiel | | 2018-07-11 | v.21 | John Hartfiel | | | v.20 | John Hartfiel | | 2018-02-08 | v.19 | John Hartfiel | | 2017-12-20 | v.14 | John Hartfiel | - Design Update
- typo correction on documentation
| 2017-11-22 | v.10 | John Hartfiel | - Update assembly versions with new Flash size
- Udate HW Table Name
- Update Design
| 2017-11-14 | v.6 | John Hartfiel | | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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