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Template Revision 2.6 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Template Revision 1.2
Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
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Overview

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General Design description
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Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).

Key Features

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Excerpt
  • TEBF0808
  • Linux
  • USB
  • ETH
  • PCIe
  • SATA
  • SD
  • I2C
  • DP
  • RGPIO
  • user LED access
  • Modified FSBL for Si5345 programming
  • Special FSBL for QSPI Programming

Revision History

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- Export PDF to download, if vivado revision is changed!
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...

  • new assembly variant

...

  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif

...

  • solved Linux Flash issue

...

  • same CLK for VIO

...

  • solved JTAG/Linux issue

...

  • initial release

Release Notes and Know Issues

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Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal

...

Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
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        Scroll Table Layout
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        ExampleComment
        12



  • ...


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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :

Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).

Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vivado 2018.3
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • DP
  • user LED access
  • Modified FSBL for Si5338 programming
  • Special FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2019-05-222018.3TE0807-StarterKit-vivado_2018.3-build_06_20190522132448.zip
TE0807-StarterKit_noprebuilt-vivado_2018.3-build_06_20190522132504.zip

  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
  • ES2 prebuilt files are not included
2019-02-072018.2TE0807-StarterKit_noprebuilt-vivado_2018.2-build_04_20190207111631.zip
TE0807-StarterKit-vivado_2018.2-build_04_20190207111616.zip
John Hartfiel
  • new assembly variant
2018-09-042018.2TE0807-StarterKit_noprebuilt-vivado_2018.2-build_03_20180904122245.zip
TE0807-StarterKit-vivado_2018.2-build_03_20180904121600.zip
John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-242017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip
TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip
John Hartfiel
  • solved Linux Flash issue
2018-02-062017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip
John Hartfiel
  • same CLK for VIO
2018-02-052017.4TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip
TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-01-182017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


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titleKnown Issues

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IssuesDescriptionWorkaround/SolutionTo be fixed version
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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titleSoftware

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SoftwareVersionNote
Vivado2018.3needed
SDK2018.3needed
PetaLinux2018.3needed
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   es2_2gb      REV01    2GB      64GB       NA         NA     Slower DDR Speed 
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      64GB       NA         NA     NA           
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      64GB       NA         NA     with heat sink   


Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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titleHardware Carrier

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Carrier ModelNotes
TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


Additional HW Requirements:

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titleAdditional Hardware

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Additional HardwareNotes



Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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titleAdditional design sources

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TypeLocationNotes
SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration
init.sh<design name>/sd/Additional Initialization Script for Linux


Prebuilt

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  • prebuilt files
  • Template Table:

    • Scroll Title
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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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titlePrebuilt files (only on ZIP with prebult content)

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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

...

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  • Important set new Vivado version link on every Design update of new vivado version!
  • Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de
/enTE080320171/Starterkit   -->

Reference Design is available on:

Design Flow

<!-- Basic Design Steps Add/ Remove project specific   -->
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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image RemovedImage Added
  2. Press 0 and enter for minimum setupto start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
  5. Create Project
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  6. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  7. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  8. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default<ddr size>" or "prebuilt\os\petalinux\<short name>"Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  9. Generate Programming Files with Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

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Note:

  • Programming

...

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<!-- Description of Block Design, Constrains... BD Pictures from Export...   -->
  • and Startup procedure

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  • Connect JTAG and power on carrier with module
  • Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  • Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

...

  •          optional "TE::pr_program_flash_binfile -swapp hello_

...

  • te0803" possible
  • Copy image.ub on SD-Card

      ...

        • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
      • Set Boot Mode to QSPI-Boot and insered SD.
        • Depends on Carrier, see carrier TRM.
        • TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

      SD

      1. Copy image.ub and Boot.bin on SD-Card.
        • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
      2. Set Boot Mode to SD-Boot.
        • Depends on Carrier, see carrier TRM.
      3. Insert SD-Card in SD-Slot.

      ...

      1. Open Serial Console (e.g. putty)
        1. Speed: 115200
        2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
      2. Linux Console:
        Note: Wait until Linux boot finished For Linux Login use:
        1. User Name: root
        2. Password: root
      3. You can use Linux shell now.
        1. I2C 0 Bus type: i2cdetect -y -r 0
        2. ETH0 works with udhcpc
        3. USB type  "lsusb" or connect USB device
        4. PCIe type "lspci"

      Vivado Hardware Manager

      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

      System Design - Vivado

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      Block Design

      Image Removed

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      Activated interfaces:

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      Constrains

      Basic module constrains

      Code Block
      languageruby
      title_i_bitgen.xdc
      set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
      set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

      Design specific constrain

      Code Block
      languageruby
      title_i_io.xdc
      
      #System Controller IP
      
      #J3:31 LED_HD
      set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
      #J3:41
      set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
      #J3:45
      set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
      #J3:47
      set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
      #J3:32
      set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
      #J3:34
      set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
      #J3:36
      set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
      #J3:38
      set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
      #J3:40
      set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
      #J3:42
      set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
      #J3:46 CAN S
      set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
      #J3:48 LED_XMOD
      set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
      #J3:50 CAN TX 
      set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
      #J3:52 CAN RX 
      set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
      
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
      
      # PLL
      #J4:74
      #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
      
      
      
      # Audio Codec
      #LRCLK        J3:49 B47_L9_N
      #BCLK        J3:51 B47_L9_P
      #DAC_SDATA    J3:53 B47_L7_N
      #ADC_SDATA    J3:55 B47_L7_P
      set_property PACKAGE_PIN G14 [get_ports LRCLK ]
      set_property PACKAGE_PIN H14 [get_ports BCLK ]
      set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
      set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
      
      

      Software Design - SDK/HSI

      HTML
      <!--
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      For SDK project creation, follow instructions from:

      SDK Projects

      Application

      SDK template in ./sw_lib/sw_apps/ available.

      FSBL

      TE modified 2018.2 FSBL

      Changes:

      • Si5345Configuration, PCIe Reset over GPIO
        • See xfsbl_board.c and xfsbl_board.h
        • Add Si5345-Registers.h, si5345.c, si5345.h

      Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

      zynqmp_fsbl_flash

      TE modified 2018.2 FSBL

      Changes:

      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

      Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL

      PMU

      Xilinx default PMU firmware.

      hello_te0807

      Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

      u-noot

      U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

      Software Design -  PetaLinux

      HTML
      <!--
      optional chapter
      Add "No changes." or "Activate: List"
         -->

      For PetaLinux installation and  project creation, follow instructions from:

      Config

      No changes.

      U-Boot

      • Change platform-top.h
      Code Block
      languagejs
      #include <configs/platform-auto.h>
      #define CONFIG_SYS_BOOTM_LEN 0xF000000
       
      #define DFU_ALT_INFO_RAM \
                      "dfu_ram_info=" \
              "setenv dfu_alt_info " \
              "image.ub ram $netstart 0x1e00000\0" \
              "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
              "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
       
      #define DFU_ALT_INFO_MMC \
              "dfu_mmc_info=" \
              "set dfu_alt_info " \
              "${kernel_image} fat 0 1\\\\;" \
              "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
              "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
       
      /*Required for uartless designs */
      #ifndef CONFIG_BAUDRATE
      #define CONFIG_BAUDRATE 115200
      #ifdef CONFIG_DEBUG_UART
      #undef CONFIG_DEBUG_UART
      #endif
      #endif
       
      /*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
      #ifdef CONFIG_ZYNQMP_EEPROM
      #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
      #define CONFIG_CMD_EEPROM
      #define CONFIG_ZYNQ_EEPROM_BUS          5
      #define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
      #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0x20
      #endif
      
      

      Device Tree

      ...

      languagejs

      ...

      1. Option Features
        1. Webserver to get access to Zynq
          1. insert IP on web browser to start web interface
        2. init.sh scripts
          1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

      Vivado Hardware Manager

      Page properties
      hiddentrue
      idComments

      Note:

      • Add picture of HW Manager

      • add notes for the signal either groups or topics, for example:

        Control:

        • add controllable IOs with short notes..

        Monitoring:

        • add short notes for signals which will be monitored only

        SI5338_CLK0 Counter: 

        Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

      • Control:
        • LEDs: XMOD 2(without green dot) and HD LED are accessible.
        • CAN_S
      Scroll Title
      anchorFigure_VHM
      titleVivado Hardware Manager


      Image Added

      Image Added


      System Design - Vivado

      HTML
      <!--
      Description of Block Design, Constrains...
      BD Pictures from Export...
        -->

      Block Design

      Scroll Title
      anchorFigure_BD
      titleBlock Design
      Image Added

      PS Interfaces

      Page properties
      hiddentrue
      idComments

      Note:

      • optional for Zynq / ZynqMP only

      • add basic PS configuration

      Activated interfaces:

      Scroll Title
      anchorTable_PSI
      titlePS Interfaces

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      TypeNote
      DDR
      QSPIMIO
      SD0MIO
      SD1MIO
      CAN0EMIO
      I2C0MIO
      PJTAG0MIO
      UART0MIO
      GPIO0MIO
      SWDT0..1
      TTC0..3
      GEM3MIO
      USB0MIO/GTP
      PCIeMIO/GTP
      SATAGTP
      DisplayPortEMIO/GTP


      Constrains

      Basic module constrains

      Code Block
      languageruby
      title_i_bitgen.xdc
      set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
      set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

      Design specific constrain

      Code Block
      languageruby
      title_i_io.xdc
      
      #System Controller IP
      
      #J3:31 LED_HD
      set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
      #J3:41
      set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
      #J3:45
      set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
      #J3:47
      set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
      #J3:32
      set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
      #J3:34
      set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
      #J3:36
      set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
      #J3:38
      set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
      #J3:40
      set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
      #J3:42
      set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
      #J3:46 CAN S
      set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
      #J3:48 LED_XMOD
      set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
      #J3:50 CAN TX 
      set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
      #J3:52 CAN RX 
      set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
      
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
      
      # PLL
      #J4:74
      #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
      
      
      
      # Audio Codec
      #LRCLK        J3:49 B47_L9_N
      #BCLK        J3:51 B47_L9_P
      #DAC_SDATA    J3:53 B47_L7_N
      #ADC_SDATA    J3:55 B47_L7_P
      set_property PACKAGE_PIN G14 [get_ports LRCLK ]
      set_property PACKAGE_PIN H14 [get_ports BCLK ]
      set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
      set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
      
      

      Software Design - SDK/HSI

      Page properties
      hiddentrue
      idComments
      Note:
      • optional chapter separate

      • sections for different apps

      For SDK project creation, follow instructions from:

      SDK Projects

      Application

      Page properties
      hiddentrue
      idComments

      ----------------------------------------------------------

      FPGA Example

      scu

      MCS Firmware to configure SI5338 and Reset System.

      srec_spi_bootloader

      TE modified 2018.3 SREC

      Bootloader to load app or second bootloader from flash into DDR

      Descriptions:

      • Modified Files: blconfig.h, bootloader.c
      • Changes:
        • Add some console outputs and changed bootloader read address.
        • Add bugfix for 2018.2 qspi flash

      xilisf_v5_11

      TE modified 2018.3 xilisf_v5_11

      • Changed default Flash type to 5.

      ----------------------------------------------------------

      Zynq Example:

      zynq_fsbl

      TE modified 2018.3 FSBL

      General:

      • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

      • General Changes: 
        • Display FSBL Banner and Device ID

      Module Specific:

      • Add Files: all TE Files start with te_*
        • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
        • CPLD access
        • Read CPLD Firmware and SoC Type
        • Configure Marvell PHY

      zynq_fsbl_flash

      TE modified 2018.3 FSBL

      General:

      • Modified Files: main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      ZynqMP Example:

      ----------------------------------------------------------

      zynqmp_fsbl

      TE modified 2018.3 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
      • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5338 Configuration
        • ETH+OTG Reset over MIO

      zynqmp_fsbl_flash

      TE modified 2018.3 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation


      zynqmp_pmufw

      Xilinx default PMU firmware.

      ----------------------------------------------------------

      General Example:

      hello_te0820

      Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

      SDK template in ./sw_lib/sw_apps/ available.

      zynqmp_fsbl

      TE modified 2018.3 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
      • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5345 Configuration
        • OTG+PCIe Reset over MIO
        • I2C MUX for EEPROM MAC

      zynqmp_fsbl_flash

      TE modified 2018.3 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      zynqmp_pmufw

      Xilinx default PMU firmware.

      hello_te0807

      Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

      Software Design -  PetaLinux

      Page properties
      hiddentrue
      idComments
      Note:
      • optional chapter separate

      • sections for linux

      • Add "No changes." or "Activate: and add List"

      For PetaLinux installation and  project creation, follow instructions from:

      Config

      Start with petalinux-config or petalinux-config --get-hw-description

      Activate:

      • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
      • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

      U-Boot

      Start with petalinux-config -c u-boot
      Changes:

      • CONFIG_ENV_IS_NOWHERE=y

      • CONFIG_ENV_IS_IN_SPI_FLASH is not set

      Change platform-top.h:

      Code Block
      languagejs
      #include <configs/platform-auto.h>
      #define CONFIG_SYS_BOOTM_LEN 0xF000000
      
      #define DFU_ALT_INFO_RAM \
                      "dfu_ram_info=" \
              "setenv dfu_alt_info " \
              "image.ub ram $netstart 0x1e00000\0" \
              "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
              "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
      
      #define DFU_ALT_INFO_MMC \
              "dfu_mmc_info=" \
              "set dfu_alt_info " \
              "${kernel_image} fat 0 1\\\\;" \
              "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
              "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
      
      /*Required for uartless designs */
      #ifndef CONFIG_BAUDRATE
      #define CONFIG_BAUDRATE 115200
      #ifdef CONFIG_DEBUG_UART
      #undef CONFIG_DEBUG_UART
      #endif
      #endif
      
      /*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
      #define CONFIG_ZYNQMP_EEPROM
      #ifdef CONFIG_ZYNQMP_EEPROM
      #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
      #define CONFIG_CMD_EEPROM
      #define CONFIG_ZYNQ_EEPROM_BUS          0
      #define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x50
      #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0xFA
      #endif
      
      

      Device Tree

      Code Block
      languagejs
      /include/ "system-conf.dtsi"
      / {
      };
      /* notes:
      serdes: // PHY TYP see: dt-bindings/phy/phy.h
      */
      
      /* default */
      
      /* SD */
      
      &sdhci1 {
      	// disable-wp;
      	no-1-8-v;
      
      };
      
      /*PCIE*/
      &pcie {
           phys = <&lane0 2 0 2 100000000>;  //not recognized at the moment on linux
      };
      
      /* DP */ 
      &zynqmp_dpsub {
          phys = <&lane3 5 0 3 27000000>; //Xilinx default is 5 (UFS), 6 (DP) does not work
      };
      
      /* SATA */
      
      &sata {
          phys = <&lane2 1 0 1 150000000>;  //TE0808,TE0807
          //phys = <&lane2 1 0 0 150000000>; //TE0803
      };
      
      
      /* USB  */
      
      
      &dwc3_0 {
          status = "okay";
          dr_mode = "host";
          snps,usb3_lpm_capable;
          snps,dis_u3_susphy_quirk;
          snps,dis_u2_susphy_quirk;
          phy-names = "usb2-phy","usb3-phy";
          phys = <&lane1 4 0 2 100000000>;
          maximum-speed = "super-speed";
      };
      
      /* ETH PHY */
       
      &gem3 {
          	phy-handle = <&phy0>;
          	phy0: phy0@1 {
              		device_type = "ethernet-phy";
              		reg = <1>;
          	};
      };
       
      /* QSPI */
       
      &qspi {
          #address-cells = <1>;
          #size-cells = <0>;
          status = "okay";
          flash0: flash@0 {
              compatible = "jedec,spi-nor";
              reg = <0x0>;
              #address-cells = <1>;
              #size-cells = <1>;
          };
      };
       
      /* I2C */
       
      &i2c0 {
          i2cswitch@73 { // u
              compatible = "nxp,pca9548";
              #address-cells = <1>;
              #size-cells = <0>;
              reg = <0x73>;
              i2c-mux-idle-disconnect;
       
              i2c@2 { // PCIe
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;
              };
              i2c@3 { // i2c SFP
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;
              };
              i2c@4 { // i2c SFP
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;
              };
              i2c@5 { // i2c EEPROM
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5>;
              };
              i2c@6 { // i2c FMC
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
       
                  si570_2: clock-generator3@5d {
                      #clock-cells = <0>;
                      compatible = "silabs,si570";
                      reg = <0x5d>;
                      temperature-stability = <50>;
                      factory-fout = <156250000>;
                      clock-frequency = <78800000>;
                  };
              };
              i2c@7 { // i2c USB HUB
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
          i2cswitch@77 { // u
              compatible = "nxp,pca9548";
              #address-cells = <1>;
              #size-cells = <0>;
              reg = <0x77>;
              i2c-mux-idle-disconnect;
              i2c@0 { // i2c PMOD
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <0>;
              };
              i2c@1 { // i2c Audio Codec
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <1>;
                  			/*
                  adau1761: adau1761@38 {
                      compatible = "adi,adau1761";
                      reg = <0x38>;
                  };
                  			*/
              };
              i2c@2 { // i2c FireFly A
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;
              };
              i2c@3 { // i2c FireFly B
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;
              };
              i2c@4 { // i2c PLL
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;
              };
              i2c@5 { // i2c SC
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5>;
              };
              i2c@6 { // i2c
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
              };
              i2c@7 { // i2c
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
      };
       
      /* UNUSED DMA disable */
       
      &lpd_dma_chan1 {
          status = "disabled";
      };
      &lpd_dma_chan2 {
      
            status = "disabled";
      };
      &lpd_dma_chan3 {
          status = "disabled"};
      };
      &lpd_dma_chan4 {
          status = "disabled";
      };
      &lpd_dma_chan5 {
          status = "disabled";
      };
      &lpd_dma_chan6 {
          status = "disabled";
      };
      &lpd_dma_chan7 {
          status = "disabled";
      };
      &lpd_dma_chan8 {
          status = "disabled";
      };
      
      

      Kernel

      Deactivate:

      • CONFIG_CPU_IDLE        (only needed to fix JTAG Debug issue)

      • CONFIG_CPU_FREQ      (only needed to fix JTAG Debug issue)

      Rootfs

      Activate:

      • i2c-tools

      Applications

      startup

      Script App to load init.sh from SD Card if available.

      See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

      adau1761init

      Audio initialisation.

      Additional Software

      HTML
      <!--
      Add Description for other Software, for example SI CLK Builder ...
       -->

      SI5345

      Download  ClockBuilder Pro for SI5345

      1. Install and start ClockBuilder
      2. Open "/misc/SI5345/Si5345-RevB-0807-02A-Project.slabtimeproj"
      3. Modify settings
      4. Export → Register File → select C code header → save to file
      5. Replace Header files from FSBL template with generated file

      Appx. A: Change History and Legal Notices

      Document Change History

      To get content of older revision  got to "Change History"  of this page and select older document revision number.

      HTML
      <!--
      Generate new entry:
      1:add new row below first
      2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
      3.Update Metadate =Page Information Macro Preview+1
        -->
      
      
      
      

      Kernel

      Start with petalinux-config -c kernel

      Changes:

      • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

      • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

      • CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)
      • CONFIG_EDAC_CORTEX_ARM64=y

      Rootfs

      Start with petalinux-config -c rootfs

      Changes:

      • CONFIG_busybox-httpd=y (for web server app)
      • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

      Applications

      startup

      Script App to load init.sh from SD Card if available.

      See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

      webfwu

      Webserver application accemble for Zynq access. Need busybox-httpd

      Additional Software

      Page properties
      hiddentrue
      idComments
      Note:
      • Add description for other Software, for example SI CLK Builder ...
      • SI5338 and SI5345 also Link to:

      SI5345

      File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

      General documentation how you work with these project will be available on Si5345

      Appx. A: Change History and Legal Notices

      Document Change History

      To get content of older revision  got to "Change History"  of this page and select older document revision number.

      Page properties
      hiddentrue
      idComments
      • Note this list must be only updated, if the document is online on public doc!
      • It's semi automatically, so do following
        • Add new row below first

        • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

        • Metadata is only used of compatibility of older exports


      ...

      Scroll Title
      anchorTable_dch
      titleDocument change history.

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths2*,*,3*,4*
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      DateDocument Revision

      Authors

      Description

      Page info
      modified-date
      modified-date
      dateFormatyyyy-MM-dd

      Page info
      infoTypeCurrent version
      prefixv.
      typeFlat

      Page info
      modified-user
      modified-user

      ...

      • new assembly variant


      • Release 2018.3

      2019-09-04

      v.13John Hartfiel
      • Release 2018.2

      2018-07-20

      ...

      v.12John Hartfiel
      • Design update

      2018-04-30

      ...

      v.10John Hartfiel
      • Update known issues

      2018-02-08

      ...

      v.9John Hartfiel
      • Design update
      2018-01-29v.4John Hartfiel
      • Update known issues
      2018-01-18v.3John Hartfiel
      • Release 2017.4

      All

      Page info
      modified-users
      modified-users



      Legal Notices

      Include Page
      IN:Legal Notices
      IN:Legal Notices

      ...