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Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 47 |
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diagramName | TEI0009_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 639 |
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Scroll Only |
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Power-On Sequence
There is no power on sequence, After power up regulators will be enabled as you can see in the diagram below.
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 26 |
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diagramName | TEI0009_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 639 |
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Scroll Only |
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Voltage Monitor Circuit
There is a diod (D12) which protects the board from wrong polarity, Additionaly there is an Over/under voltage (IC) which protects the board from over voltage damages.
Scroll Title |
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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draw.io Diagram |
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border | true |
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viewerToolbar | true |
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fitWindow | false |
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diagramName | TEI0009_PWR_VM |
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simpleViewer | false |
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width | |
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diagramWidth | 641 |
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revision | 1 |
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Scroll Only |
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Image Added | Create DrawIO object here: Attention if you copy from other page, objects are only linked. | Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Designator | VCC / VCCIO Schematic Name | Pin | Direction | Notes |
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J3 | 3.3V | 2,4 | Out |
| 5V | 5 | Out |
| J5 | 3.3V | 3 | Out |
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank 1 | VCCIO1 | 3.3V |
| Bank 2 | VCCIO2 | 3.3V |
| Bank 3 | VCCIO3 | 3.3V |
| Bank 4 | VCCIO4 | 3.3V |
| Bank 5 | VCCIO5 | 3.3V |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 7 | VCCIO7 | 3.3V |
| Bank 8 | VCCIO8 | 3.3V |
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Technical Specifications
Absolute Maximum Ratings
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