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Template Revision 2.9
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Important General Note:
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Table of Contents |
Overview
The Cyclone10 LP Reference Kit is the world's first development board with a 55kLE Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.
Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.
Key Features
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Note: 'Key Features' description: Important components and connector or other Features of the module → please sort and indicate assembly options |
- Intel® Cyclone 10 LP [10CL055YU484C8G],
- Package: UBGA-484
- Speed Grade: 8 (Slowest)
- Temperature: 0°C ~ 85°C
- Package compatible device 10CL016, 10CL040, 10CL080 as assembly variant on request is possible
- 16 MBit flash memory (optional up to 32 MBit possible)
- Integrated USB2.0 Programmer
- Pin Header connectors
- 256 MBit (optional up to 512 MBit possible) SDRAM
- 128 MBit (optional up to 512 MBit possible) User Quad-SPI Flash memory
- 64 MBit HyperRAM(Pseudo SRAM) (optional up to 128 MBit possible)
- FTDI - System Controller (CPLD)
- 2x MAC address EEPROM
- 2x Fast Ethernet PHY (10/100 Mbps)
- 8-channel, 12-bit, configurable ADC /DAC with on-chip reference
- D-Sub connector
- 2x RJ45 connector
- LEDs:
- Status LEDs, Power LED
- 13x User LEDs
- 7-segment display
- Push bottuns:
- 2x Reset Push buttons
- 5x User Push buttons
- I/O:
- Power Supply:
- Others:
- Reverse polarity of supply voltage protection
- Under/Over voltage protection
Block Diagram
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
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title | TEI0009 main components |
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- Barrel Jack, J12
- RJ45 socket, J8...9
- D-Sub Connector, J11
- Push button(Reset), S7
- Grove connector, J5
- Under/Over Voltage Protecter, U9
- 7-segment LED, D11
- 1x6 pin header, J4
- 1x8 pin header, J2...3
- User Red LEDs, D2...9
- 8x User Red LEDs, D13...17
- 5x User Push buttons, S1- S3...6
- Red LED (CONF_DONE), D10
- PSRAM memory, U3
- SDRAM memory, U10
- Voltage Regulator, U5- U7
- AD/DA Convertor, U2
- Pmod 2x6 SMD host socket, P1...6
- Intel®Cyclone 10 LP, U1
- Configuration memory, U5
- 1x10 pin header, J1
- EEEPROM, U15- U18- U20
- FTDI USB2 to JTAG/UART adapter, U14
- Micro USB 2.0 (receptacle) J10
- Push button (RST_GPIO), S2
- Oscillator, U22
- Ethernet PHY, U17- U19
- QSPI Flash memory, U12
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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Storage device name | Content | Notes |
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QSPI Flash | Not programmed |
| EEPROM | Programmed | FTDI configuration | SDRAM | Not programmed |
| PSRAM | Not programmed |
| FTDI System Controller CPLD | Not programmed |
| Configuration Memory | Demo Design |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Configuration mode has been set to AS (Active Serial) configuration.
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anchor | Table_OV_BP |
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title | Boot process. |
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MODE Signal State | MSEL0 | MSEL1 | MSEL2 | MSEL3 | Connected to | Boot Mode |
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MSEL[0:3] | 0 | 1 | 0 | 0 | Bank 6 | AS (Active Serial) |
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RESET pin can be set through the push button S1.
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal | Connected to | Note |
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RESET | S7 (Push button) | Connected to nCONFIG | RST_GPIO | S2 (Push button) |
| EXT_RST | J3 (1x8 pin header) Bank 2 |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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I/Os on Pin Headers and Connectors
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
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Bank 1 | J1 (Pin header) | 8 Single ended | 3.3 V |
| J2 (Pin header) | 8 Single ended | 3.3 V |
| J4 (Pin header) | 6 Single ended | 3.3 V |
| Bank 2 | J3 (Pin header) | 1 Single ended | 3.3 V |
| P1 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P2 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| J11 (VGA host Socket) | 14 Single ended | 3.3 V |
| Bank 6 | J5 (Grove connector) | 2 Single ended | 3.3 V |
| Bank 7 | P5 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P6 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| Bank 8 | P3 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| P4 (PMod SMD host socket) | 8 Single ended | 3.3 V |
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PMod SMD Host Socket
TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP (U1).
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anchor | Table_SIP_SMD |
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title | PMod SMD host socket information |
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orientation | portrait |
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sortDirection | ASC |
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Designator | Signals | Connected to | Notes |
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P1 | P1_IO1...8 | Bank 2 |
| P2 | P2_IO1...8 | Bank 2 |
| P3 | P3_IO1...8 | Bank 8 |
| P4 | P4_IO1...8 | Bank 8 |
| P5 | P5_IO1...8 | Bank 7 |
| P6 | P6_IO1...8 | Bank 7 |
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UART Interface
UART access to TEI0009 is available on 1x8 pin header J2.
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anchor | Table_SIP_UART |
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title | UART interface information |
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orientation | portrait |
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sortDirection | ASC |
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Schematic | Pin Header | Connected to | Voltage Level | Notes |
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TXD | J2 | Bank 1 | 3.3 V |
| RXD | J2 | Bank 1 | 3.3 V |
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Micro USB2.0 Connector
U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).
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anchor | Table_SIP_USB |
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title | Micro USB2.0 B Receptacle 90 ° information |
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orientation | portrait |
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sortDirection | ASC |
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Schematic | Connected to | Voltage Level | Notes |
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USB_VBUS | GND |
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| D- | U14 (FTDI FT2232) | 3.3 V |
| D+ | U14 (FTDI FT2232) | 3.3 V |
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RJ45 Connectors
TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .
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anchor | Table_SIP_RJ45 |
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title | RJ45 connectors information |
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orientation | portrait |
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sortDirection | ASC |
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Pin | Schematic | ETH1 Pin | ETH2 Pin | Notes |
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TD+ | ETH_TX_P | U17- TXP | U19- TXP |
| CT | ETH_CTREF_TCT | - | - | Connected to GND | TD- | ETH_TX_N | U17- TXM | U19- TXM |
| RD+ | ETH_RX_P | U17- RXP | U19- RXP |
| CT | ETH_CTREF_RCT | - | - | Connected to GND | RD- | ETH_RX_N | U17- RXM | U19- RXM |
| LED Green | ETH_LED0 | U17- NWAYEN | U19- NWAYEN |
| LED Yellow | ETH_LED1 | U17- SPEED | U19- SPEED |
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D-Sub Connectors
TEI0009 is equipped with a D-Sub connector (Receptacle) which provides interface to Cyclone 10 LP through Bank 2.
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anchor | Table_SIP_VGA |
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title | VGA host socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Corresponding Signals | Connected to | Notes |
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VGA_RED | VGA_R0...3 | Bank 2 | Red channel | VGA_GREEN | VGA_G0...3 | Bank 2 | Green channel | VGA_BLUE | VGA_B0...3 | Bank 2 | Blue channel | VGA_RGB_HSYNC | VGA_HS | Bank 2 | Horizontal sync | VGA_RGB_VSYNC | VGA_VS | Bank 2 | Vertical sync |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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QSPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
There is a 64MBit QSPI Flash memory (U12) provided by Winbond which can be used to store data or configuration.
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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CS | F_CS | Bank 7 |
| CLK | F_CLK | Bank 7 |
| IO0...3 | F_IO0...3 | Bank 7 |
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SDRAM Memory
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0009 has 256 MBit volatile provided by Winbond , SDRAM IC(U10) for storing user application code and data. Up to 512 MBit SDRAM is possibleon other assembly option.
PSRAM Memory
The TEI0009 is integrated with 64Mbit Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation.
7 Segment LED
The TEI0009 has a LED 7 Segment- 4 Digit which is connected to Bank 6.
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anchor | Table_OBP_7SEG |
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title | LED 7 Segment pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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A/L1 | SEG_CA | Bank 6 |
| B/L2 | SEG_CB | Bank 6 |
| C/L3 | SEG_CC | Bank 6 |
| D | SEG_CD | Bank 6 |
| E | SEG_CE | Bank 6 |
| F | SEG_CF | Bank 6 |
| G | SEG_CG | Bank 6 |
| DP | SEG_CDP | Bank 6 |
| A1 | SEG_AN | Bank 6 |
| A2 | SEG_AN4 | Bank 6 |
| A3 | SEG_AN3 | Bank 6 |
| A4 | SEG_AN2 | Bank 6 |
| L1-L3 | SEG_AN1 | Bank 6 |
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FTDI FT2232
The FTDI chip U14 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.
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anchor | Table_OBP_FTDI |
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title | FTDI chip interfaces and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
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ADBUS0 | TCK | Bank 1 | JTAG interface | ADBUS1 | TDI | Bank 1 | ADBUS2 | TDO | Bank 1 | ADBUS3 | TMS | Bank 1 | BDBUS0 | BDBUS0 | Bank 6 |
| BDBUS1 | BDBUS1 | Bank 6 |
| BDBUS2 | BDBUS2 | Bank 6 |
| BDBUS3 | BDBUS3 | Bank 6 |
| BDBUS4 | BDBUS4 | Bank 6 |
| BDBUS5 | BDBUS5 | Bank 6 |
| EECS | EECS | U15 (EEPROM) |
| EECLK | EECLK | U15 (EEPROM) |
| EEDATA | EEDATA | U15 (EEPROM) |
| OSCI | CK12M | U16 (12MHz Oscillator) |
| DM | D_N | J10 (Micro USB2.0) |
| DP | D_P | J10 (Micro USB2.0) |
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Configuration Memory
On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.
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anchor | Table_OBP_EEP |
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title | FTDI and EEPROM pin connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Configuration Memory Pin | Signal Schematic Name | Connected to | Notes |
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DATA1 | AS_DATA0 | U1, Bank 1
| Data out | DATA0 | AS_ASDO | U1, Bank 1 | Data in | nCS | AS_NCS | U1, Bank 1 | chip select | DCLK | AS_DCLK | U1, Bank 1 | clock |
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Ethernet PHY
The TEI0009 is equipped with two Ethernet PHY (U19, U17) which are connected to two RJ45 connectors.
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anchor | Table_OBP_ETH |
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title | Ethernet PHY connections and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Ethernet PHY Pin | Signal Schematic Names | ETH 1 | ETH 2 | Note |
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TXD0...3 | ETH_TXD0...3 | Bank 5 | Bank 5 |
| TXC | ETH_TXC | Bank 5 | Bank 5 |
| TXEN | ETH_TXEN | Bank 5 | Bank 5 |
| RXD0...3 | ETH_RXD0...3 | Bank 5 | Bank 5 |
| RXC//B-CAST_OFF | ETH_RXC | Bank 5 | Bank 5 |
| RXER/ISO | ETH_RXER | Bank 5 | Bank 5 |
| INTRP//NAND_Tree | ETH_INTRP | Bank 5 | Bank 5 |
| XI | ETH_CLKIN | U22 (Oscillator) | U22 (Oscillator) |
| MDC | ETH_MDC | Bank 5 | Bank 5 |
| MDIO | ETH_MDIO | Bank 5 | Bank 5 |
| COL/CONFIG0 | ETH_COL | Bank 5 | Bank 5 |
| CRS/CONFIG1 | ETH_CRS | Bank 5 | Bank 5 |
| RXDV/CONFIG2 | ETH_RXDV | Bank 5 | Bank 5 |
| LED0/NWAYEN | ETH_LED0 | Bank 5 J8B (RJ45- Green LED) | Bank 5 J9B (RJ45-Green LED) |
| LED1/SPEED | ETH_LED1 | Bank 5 J8C (RJ45-Yellow LED) | Bank 5 J9B (RJ45-Yellow LED) |
| nRST | ETH_RST | Bank 5 | Bank 5 |
| RXM | ETH_RX_N | J8 (RJ45) | J9 (RJ45) |
| RXP | ETH_RX_P | J8 (RJ45) | J9 (RJ45) |
| TXM | ETH_TX_N | J8 (RJ45) | J9 (RJ45) |
| TXP | ETH_TX_P | J8 (RJ45) | J9 (RJ45) |
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EEPROM
TEI0009 has three EEPROM, U15, U18 and U20. U15 is pre-programmed by FTDI FT2232H configuration.
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anchor | Table_OBP_EEP |
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title | FTDI and EEPROM pin connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | EEPROM Pin | Signal Schematic Names | Connected to | Notes |
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U15 | CS | EECS | U14 (FTDI) |
| CLK | |EECLK | U14 (FTDI) |
| DIN/DOUT | EEDATA | U14 (FTDI) | FTDI Configuration |
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Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Pin | Schematic | Connected to | Grove Header | Notes |
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U18, U20 | SCL | I2C_SCL | Bank 6 | J5 |
| SDA | I2C_SDA | Bank 6 | J5 |
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Scroll Title |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C Address | Designator | Notes |
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0x50 | U18 |
| 0x52 | U20 |
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ADC/DAC
The TEI0009 module is equipped with 12bit ADC/DAC (U2).
Scroll Title |
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anchor | Table_OBP_A2D |
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title | ADC/DAC interface and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pins | Schematic | Connected to | Notes |
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nRESET | ADDA_RSTN | U1, Bank 2 | VREF_ADC | nSYNC | ADDA_SYNC | U1, Bank 2 |
| SCLK | MCLK | U1, Bank 2 |
| SDI | MSDI | U1, Bank 2 |
| SDO | MSDO | U1, Bank 2 |
| VREF | - | U1, Bank 2 | External reference is 1 V to 3.3V Internal reference is 2.5 V | IO0...5 | AIN0...5 | U1, Bank 1 J4, Pin header |
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LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Designator | Color | Connected to | Active Level | Note |
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LED1...8 | D2...9 | Red | Bank 3 | High |
| LED_PB1 | D13...17 | Red | Bank 7 | High |
| CONF_DONE | D10 | Red | Bank 6 | Low |
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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U22 | MEMS Oscillator | 25 MHz |
| U16 | MEMS Oscillator | 12 MHz |
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Power and Power-On Sequence
Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 1A for system startup is recommended.
Power Consumption
Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA | Typical Current |
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Intel Cyclone 10 LP FPGA | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 7 |
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diagramName | TEI0009_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 639 |
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Scroll Only |
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Power-On Sequence
There is no power on sequence, After power on, all regulators will be enabled as you can see in the diagram below.
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 6 |
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diagramName | TEI0009_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 639 |
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Scroll Only |
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Voltage Monitor Circuit
There is a diod (D12) which protects the board from reverse polarity, Additionaly there is an Over/under voltage (IC) which protects the board from over voltage damages.
Scroll Title |
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 1 |
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diagramName | TEI0009_PWR_VM |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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Scroll Only |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Designator | VCC / VCCIO Schematic Name | Pin | Direction | Notes |
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J3 | 3.3V | 2,4 | Out |
| 5V | 5 | Out |
| J5 | 3.3V | 3 | Out |
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank 1 | VCCIO1 | 3.3V |
| Bank 2 | VCCIO2 | 3.3V |
| Bank 3 | VCCIO3 | 3.3V |
| Bank 4 | VCCIO4 | 3.3V |
| Bank 5 | VCCIO5 | 3.3V |
| Bank 6 | VCCIO6 | 3.3V |
| Bank 7 | VCCIO7 | 3.3V |
| Bank 8 | VCCIO8 | 3.3V |
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Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit | Note |
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VIN | Input supply voltage | -5.0 | 5.0 | V |
| VCCIO | I/O buffers power supply | -0.5 | 3.75 | V |
| VCCINT | Core voltage | -0.5 | 1.8 | V |
| VCCD_PLL | PLL digital power supply | -0.5 | 1.8 | V |
| VCCA | Phase-locked loop (PLL) analog power supply | -0.5 | 3.75 | V |
| V_AN | Analog Input Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V |
| V_DIG | Digital Input Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V |
| V_REF_IN | Internal Reference Voltage Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V |
| V_REF_EX | External Reference Voltage Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V |
| T_STG | Storage Temperature | -35 | 85 | °C | See LTC2623WC datasheet |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN | 4.75 | 5.25 | V |
| VCCIO | 3.135 | 3.465 | V | See Cyclone 10 LP datasheet. | VCCINT | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. | VCCD_PLL | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. | VCCA | 2.375 | 2.625 | V | See Cyclone 10 LP datasheet. | V_AN | 0 | 3.3 | V | See AD5592RBCPZ datasheet. | V_DIG | 0 | 3.3 | V | See AD5592RBCPZ datasheet. | V_REF_IN | 1 | 3 | V | See AD5592RBCPZ datasheet. | V_REF_EX | 2.45 | 2.55 | V | See AD5592RBCPZ datasheet. | T_OP | 0 | 70 | °C | See SDRAM W9864G6JT datasheet |
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Physical Dimensions
Scroll Title |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 2 |
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diagramName | TEI0009_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 640 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
Scroll Title |
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Document Link |
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2018-2-19 | 01 | - | REV01 | 2018-7-18 | 02 | - Change J5 from SMD connector to GROVE connector
- Connect clock 12 MHz to Bank 1
- Connect I2C SLA/SDA to Bank 3
- Remove SMA Coaxial straight J19,J20
- Remove DIP Switch S1
- Add 5 red LEDs
- Add 2 Push buttons
- Add 64 Mbit QSPI flash memory
- Change SDRAM memory, 143 MHz to 166 MHz
- Remove 10bit ADC
- Remove 10bit DAC
- Add 12bit DAC/ADC
- Remove SMA Coaxial straight J19,J20
- Remove SMA Coaxial straight J19,J20
- Remove Tranciever USB
- Remove DIP switch S2
- Different Power Dependencies
- Remove 24MHz Oscillator
- Add 4x Pmod SMD host socket
| REV02 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Scroll Title |
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 2 |
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diagramName | TEI0009_RV_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 196 |
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Scroll Only |
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Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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