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Intel® MAX 10 Commercial [10M08SAU169C8G]
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO
Power Supply:
Dimension: 86.5mm x 25mm
Others:
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0015 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 2327 |
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| diagramName | TEI0015_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 643642 |
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| Scroll Only |
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Main Components
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SMA Connector, J5...6
Amplifier, U12 - U14 - U6
Series Voltage Reference, U8
Analog to Digital ConvertorConverter, U15
Voltage Regulator, U10 - U13 - U16
Switching Voltage Regulator, U11 - U4
SDRAM Memory, U2
- Intel® MAX 10, U1
Active serial SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
4Kb EEPROM, U9
Configuration LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB2 Receptacle, J9
1x14 pin header header, J2 (Not assembled), J2
1x6 pin header header, J4 (Not assembled), J4
Jumper, J3
1x14 pin header header, J1 (Not assembled), J1
Initial Delivery State
| Page properties |
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OBP_IOs |
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| title | FPGA I/O Banks |
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| FPGA Bank | I/O Signal Count | Connected to | Notes |
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| Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 | | 1 | Jumper, J3 | AIN7 | | Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK | Bank 2
| 4 | 1x14 Pin header, J1 | D2...5 | | 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | | 1 | 12MHz Oscillator, U7 | CLK12M | | 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | | Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD | | Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 | | 2 | 1x14 Pin header, J1 | DIO0...1 | | 1 | D12_R | DIO12 | | Bank 6 | 16 | SDRAM, U2 | DQ0...15 | | 2 | SDRAM, U2 | DQM0...1 | | 1 | D11_R | DIO11 | Bank 8
| 8 | User Red LEDs, D2...9 | LED0...7 | | 6 | SPI Flash, U5 | F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn | | 1 | Red LED, D10 | CONF_DONE | | 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | | 1 | Push Button, S2 | USER_BTN |
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Micro-USB2
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Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
| Scroll Title |
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| anchor | Table_OBP_USB |
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| title | Micro USB-2 connector pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pins | Connected to | Note |
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| VBUS | USB_VBUS | It is connected to GND |
| | D+ | FTDI FT2232H U3, DP pin |
| | D- | FTDI FT2232H U3, DM pin |
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| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Pin Header Connector | Note |
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| TMS | J4-6 |
| | TDI | J4-5 |
| | TDO | J4-4 |
| | TCK | J4-3 |
| | JTAG_EN | J4-2 | Connected Pulled-up to 3.3V |
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On-board Peripherals
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| Scroll Title |
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| anchor | Table_OBP_SDRAM |
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| title | SDRAM interface IOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
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| Address inputs | A0 ... A13 | bank 3 | - | | Bank address inputs | BA0 / BA1 | bank 3 | - | | Data input/output | DQ0 ... DQ15 | bank 6 | - | | Data mask | DQM0 ... DQM1 | bank 6 | - | | Clock | CLK | bank 3 | - | | Control Signals | CS | bank 3 | Chip select | CKE | bank 3 | Clock enable | RAS | bank 3 | Row Address Strobe | CAS | bank 3 | Column Address Strobe | | WE | bank 3 | Write Enable |
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| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D2...9 | Red | LED1...8 | Active High | User LEDs | | D10 | Red | CONF_DONE | Active Low | Configuration DONE LED | | D1 | Green | 3.3V | Active High | After power on it will be on. |
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Push Bottuns
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board Push Buttons |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected to | Functionality | Note |
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| S1 | RESET | General reset |
| | S2 | USER_BTN | User push button | Connected to FPGA Bank 8. |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Source | Schematic Name | Frequency | Note |
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| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3. Connected to FPGA SoC bank 2, pin H6. |
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Power and Power-On Sequence
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| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | TEI0015_PWR_P |
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| lbox | true |
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| revision | 1112 |
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| diagramName | TEI0015_PWR_PD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 638 |
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| Scroll Only |
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There is no specific or special power-on sequence, just one single power source is needed. After power on the Green green LED (D1) will be on.
Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Designator| VCC / VCCIO Schematic Name | VoltageJ2 Pin | Connector J9 Pin | Direction | Notes |
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| VIN | J2-13 |
VIN5V | 3.3V| 5 V - Pin Header | | 3.3V | J2-12 | - | Output |
| | 5V | J2-14 |
5VJ95V| J9-1 | Input | 5 V - USB Connector |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Intel MAX 10 SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| Bank 1A | VCCIO1A | 3.3V |
| | Bank 1B | VCCIO1B | 3.3V |
| | Bank 2 | VCCIO2 | 3.3V |
| | Bank 3 | VCCIO3 | 3.3V |
| | Bank 5 | VCCIO5 | 3.3V |
| | Bank 6 | VCCIO6 | 3.3V |
| | Bank 8 | VCCIO8 | 3.3V |
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| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | Absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit | Reference Document |
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VIN | Supply voltage | 4.75 | 5.25 | V | | VCC_ONE | Supply voltage for core and periphery through on-die voltage
regulator | -0.5 | 3.9 | V | Intel MAX 10 datasheet | | VCCIO | Supply voltage for input and output bufferse | -0.5 | 3.9 | V | Intel MAX 10 datasheet | | VCCA | Supply voltage for phase-locked loop (PLL) regulator and ADC | -0.5 | 3.9 | V | Intel MAX 10 datasheet | | V_AN_IN | Analog Input Voltage on ADC IC U15 pins | –0.3 | 5.4 | V | AD4003BCPZ datasheet | | V_REF | Analog reference voltage on IC U15 | -0.3 | 6 | V | AD4003BCPZ datasheet |
| | CH1-, CH1+ | Analog input voltage on amplifier U12 pin 1, 10 | -30 | 30 | V | AD8251 datasheet | T_STG | Storage Temperature | CH1+ | Analog input voltage on amplifier U12 pin 10 | 25 | V | AD8251ARMZ datasheet | CH1- | Analog input voltage on amplifier U12 pin 1 | -25 | V | AD8251ARMZ datasheet | T_STG | Storage Temperature | -25 | +85 | °C |
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Recommended Operating Conditions
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Max | Unit | Reference Document | VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | | VCC_ONE | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | | VCCIO | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | | VCCA | 3.135 | 3.456 | V | see Intel MAX 10 datasheet | | V_AN_IN | -0.1 | 5.1 | V | see AD4003BCPZ datasheet | V_REF | 2.4 | 5.1 | V | | Max | Unit | Reference Document |
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VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V |
| | Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+) | -10 | 10 | V | AD8251 |
see AD4003BCPZ | datasheet | T_OP | 0 | +70 | °C | W9864G6JT-6 datasheet |
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Physical Dimensions
Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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| | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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