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 Storage device name

Content

Notes

User configuration EEPROMs with MAC address (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)

Not programmed

available since PCB REV02

SPI Flash main array

Not programmed

-

eFUSE Security

Not programmed

-
Si5338A programmable PLL NVM OTPNot programmed-

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Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information, if the specific Zynq UltraScale+ MPSoC chip on module supports the maximum data transmission rate of 2400 MByte/s.

Programmable PLL Clock Generator

Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and outputs:

Configuration EEPROMs

The TE0803 (PCB REV02 or newer) contains EEPROMs for general user purposes and mac address. The EEPROMs are provided by Microchip and all have I²C interfaces:

EEPROM ModellSchematic DesignatorMemory DensityPurpose
24AA025E48T-I/OTU412 Kbituser

Table 21:  On-board configuration EEPROMs overview

Programmable PLL Clock Generator

Following table illustrates on-board Si5338A programmable clock multiplier chip inputs and outputs:

InputConnected toInputConnected toFrequencyNotes
IN1 / IN2B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN3On-board Oscillator (U6)25.000000 MHz-
OutputConnected toFrequencyNotes
CLK0 A/BB2B Connector pins J2-1, J2-3 (differential pair)UserDefault off
CLK1 A/BB224 CLK1 (only available at ZU5EV MPSoC)UserDefault off
CLK2 A/BB505 CLK3UserDefault off
CLK3 A/BB505 CLK2UserDefault off

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20161223
 DateRevisionNotesLink to PCNDocumentation Link
2019-03-1803
  • Added support of DDP DDR4
  • Added support of Low power FPGA (-L1/L2).
  • Revised testpoints
  • Revised J1-J4 connectors net label style
TE0803 Product Change NotificationsTE0803-03
2018-07-1902
  • Added LDO to DDR_PLL
  • All differential pairs wath length matched with tollerance 0.1mm (excluding package delays)
  • Added MAC EEPROM U28
  • VPS_MGTRAVCC set to 0.85V
  • Added pull-up resistors R68,R69
TE0803 Product Change NotificationsTE0803-02
2016-12-2301First production release-TE0803-01First production release-TE0803-01

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

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 DateRevisionContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • add eeprom section
  • update PCB Revision section
2019-06-19v.33John Hartfiel
  • update links
  • correction flash section

2018-08-20

Aug 2018

v.29John Hartfiel
  • power section: add missing PS_1V8 output pin

2018-08-06

Aug 2018

v.28John Hartfiel
  • typo correction
2017-11-13v.23Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13

v.19



John Hartfiel
  • rework B2B section
2017-10-19

v.18

John Hartfiel
  • Removed ES1 Note
2017-08-15v.17Vitali Tsiukala
  • Changed Signals Count in the table B2B-connectors

2017-08-07


v.14

Jan Kumann
  • New smaller images.
  • New QSPI Flash MIO mapping table.
  • Temperature information changes.
  • Few corrections.

2017-05-17

V.4


Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.

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