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Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Quad SPI Flash Memory
Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Scroll Title |
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anchor | Table_OBP_CLK_GEN |
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title | Clock Generator Connections and Pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Clock Generator Pin | Signal Schematic Names | Connected to | Note |
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REFP | - | Pin 3, U43 (Oscillator) |
| REFSEL | REFSEL | - | Pulled-up to +3.3V | RESETN/SYNC | CLK_GEN_RESET | Pin B5, FPGA Bank 26 | Pulled-up to +3.3V | EEPROMSEL | EEPROMSEL | - | Pulled-up to +3.3V | SDA/GPIO2 | CLK_GEN_SDA | - (Default), MIO9, FPGA Bank 500 (R185/196 required), Pin 2, J14 (Pin Header required) | Pulled-up to +3.3V, (Default) Pulled-up to +3.3V, Pulled-up to +3.3V | SCL/GPIO3 | CLK_GEN_SCL | - (Default), MIO8, FPGA Bank 500 (R185/196 required), Pin 3, J14 (Pin Header required) | Pulled-up to +3.3V, (Default) Pulled-up to +3.3V, Pulled-up to +3.3V | OE/GPIO4 | - | - | Pulled-up to +3.3V | Y1P | CLK_Y1_P / CLK_DP_P | Pin G19, FPGA Bank 505 | 27 MHz | Y1N | CLK_Y1_N / CLK_DP_N | Pin G20, FPGA Bank 505 | 27 MHz | Y1N | CLK_Y1_N | Y2P | CLK_Y2_P / CLK_USB_P | Pin J19, FPGA Bank 505 | 26 MHz | Y2N | CLK_Y2_N / CLK_USB_N | Pin J20, FPGA Bank 505 | 26 MHz | Y3P | CLK_Y3_P / CLK_PCIe_P | Pin L19, FPGA Bank 505 | 100 MHz | Y3N | CLK_Y3_N | Y4P | / CLK_Y4_P | Y4N | CLK_Y4_N | PCIe_N | Pin L20, FPGA Bank 505 | 100 MHz | Y4P | CLK_Y4_P / SSD_RCLK_P | Pin 55, U5 (M.2) | 100 MHz | Y4N | CLK_Y4_N / SSD_RCLK_N | Pin 53, U5 (M.2) | 100 MHz |
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Oscillators
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Oscillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Signal Schematic Names | Connected to | Description | Frequency | Note | U43
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U7 | ETH_XTAL_IN | Pin 34, U6 (Ethernet PHY) | Clock for | Clock GeneratorEthernet | 25 MHz |
| U15 | 33 MHz | U7 | 25 MHz | PS_CLK | Pin H14, FPGA Bank 503 | Clock for FPGA | 33 MHz |
| U23 | USB_CLK / USB0_RCLK | Pin 26, U22 (USB PHY)U23 | Clock for USB | 52 MHz |
| U43 | - | Pin 5, U8 (Clock Generator) | Clock for Clock Generator | 25 MHz |
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7-Segment Display
The TEI0802 has a 4-Digit-7-Segment LED display.
Scroll Title |
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anchor | Table_OBP_7SEG |
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title | 7-Segment LED Pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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A/L1 | CA / SEG_CA | Pin E4, FPGA Bank 65 |
| B/L2 | CB / SEG_CB | Pin D3, FPGA Bank 65 |
| C/L3 | CC / SEG_CC | Pin N5, FPGA Bank 65 |
| D | CD / SEG_CD | Pin P5, FPGA Bank 65 |
| E | CE / SEG_CE |
F | Pin N4, FPGA Bank 65 |
| F | CF / SEG_CF | Pin C3, FPGA Bank 65 |
| G | CG / SEG_CG | Pin R5, FPGA Bank 65 |
| DP | CDP / SEG_CDP | Pin N3, FPGA Bank 65 |
| A1 | SEG_ | ANAN1 | Pin A9, FPGA Bank 26 |
| A2 | SEG_ | AN4AN2 | Pin B9, FPGA Bank 26 |
| A3 | SEG_AN3 | Pin A7, FPGA Bank 26 |
| A4 | SEG_ | AN2AN4 | Pin B6, FPGA Bank 26 |
| L1-L3 | SEG_ | AN1
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User LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Color | Connected to | Active Level | Note |
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LED0...7 | Red | Bank 65 | High |
| D12 | Green | U9, PMIC | High |
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Scroll Title |
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anchor | Table_OBP_PBTN |
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title | On-board Push Buttons |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | SchematicDesignator | Connected to | Functionality | Note |
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BTN_1 | USER_BTN_UP | Pin U2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | BTN_2 | RESET | Bank | Reset | RST_GPIO | Bank | Reset/GPIO | USER_BTN_LEFT | Pin R1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | BTN_3 | USER_BTN_UP | Bank | User Push Button | USER_BTN_OK | Pin T1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | BTN_4 | USER_BTN_RIGHT | Pin U1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | BTN_5 | USER_BTN_DOWN | BankPin T2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | BTN_6 | POR_B | Pin 38, U1 (PMIC), Pin 38, U9 (PMIC), Pin K12, FPGA Bank 503 | Reset Button | Pulled-up to +3.3V. |
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DIP Switch
Scroll Title |
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anchor | Table_OBP_DIP_SWITCH |
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title | DIP Switch S1 |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | SchematicColor | Connected to | Active LevelFunctionality | Note |
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Scroll Title |
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anchor | Table_OBP_SWITCH |
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title | Switch |
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MODE0 | Pin J16, FPGA Bank 503 | DIP | Pulled-down to GND. | S1B | MODE1 | Pin H15, FPGA Bank 503 | DIP | Pulled-down to GND. | S1C | USER_CFG0 | Pin A4, FPGA Bank 66 | DIP | Pulled-down to GND. | S1D | USER_CFG1 | Pin B4, FPGA Bank 66 | DIP | Pulled-down to GND. | S7A | USER_SW7 | Pin M5, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7B | USER_SW6 | Pin M4, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7C | USER_SW5 | Pin J2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S7D | USER_SW4 | Pin K1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8A | USER_SW3 | Pin L1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8B | USER_SW2 | Pin M1, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8C | USER_SW1 | Pin P2, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. | S8D | USER_SW0 | Pin P3, FPGA Bank 65 | DIP | Pulled-up to +1.8V_PL. |
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Color | Connected to | Active Level | Note |
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Power and Power-On Sequence
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