Page History

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• Xilinx Zynq UltraScale+ MPSoC (XCZU2CG / XCZU2EG, XCZU3CG / XCZU3EG or XCZU4CG / XCZU4EV)
  • Quad-core or dual-core Cortex-A53 64-bit ARM v8 application processing unit (APU) (depends on assembly variant CG,EG,EV)
  • Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)

  • Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:

    • PCI Express® interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
  • 132 x HP PL I/Os (3 banks)
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
  • 4 x serial PS GTR transceivers
• 2 GByte DDR4 SDRAM, 32bit databus-width
• 128 MByte QSPI boot Flash in dual parallel mode
• 4 8 GByte eMMC
• Programmable quad PLL clock generator PLL for PS GTR clocks (optional external reference)
• Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
• MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
• Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  
• Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
• All power supplies on board
• Size: 50 x 40 mm

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1. Xilinx Zynq UltraScale+ MPSoC, U1
2. 1.8V, 512 Mbit QSPI flash memory, U7
3. 1.8V, 512 Mbit QSPI flash memory, U17
4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
11. 4 8 GByte eMMC memory, U6
12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
13. I²C programmable, any  frequency , any output  quad clock generator, U10
14. Highly integrated full featured hi-speed USB 2.0 ULPItransceiver, U18
15. LED D1(Red) Done Pin
16. LED D2 (Green) CPLD Status, User LED
    
17. LED D3 (Red) PS Error
    
18. LED D4 (Green) PS Error Status
    

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eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips MTFC4GACAJCNIS21ES08G-4M IT JCLI (FLASH - NAND Speicher-IC 32 (64 Gb (4 G x 81) MMC ) is used.

DDR4 Memory

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Two quad SPI compatible serial bus flash N25Q512A flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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v.74

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