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Scroll Title
anchorFigure_OV_BD
titleTE0745 block diagram


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Main Components

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BOOTMODE is connected to MIO4 and B2B Connector J2 (Pin 133) and BOOTMODE_1 is connected to MIO5 and System Controller CPLD and default high.

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titleBoot process.

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B2B J2-133 BOOTMODE

Boot Mode

BOOTMODE_1 (MIO5)

 BOOTMODE (MIO4)

Note

JTAG Boot mode

00

JTAG only is only  possible with other CPLD Firmware

----01not supported
QSPI10
SD Card11



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titleControl Pins

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Signal

B2BDirectionNote
RST_IN_NJ2-131InputLow-active Power-On reset pin, controls POR_B-signal (Bank 500 - C23)
PS_SRSTJ2-152InputLow-active PS system-reset pin of Zynq chip.
JTAG_ENJ1-148InputLow FPGA access, high CPLD access


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Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


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The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.

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Scroll Title
anchorFigure_PWR_VMC
titleVoltage Monitor Circuit


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Power Rails

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Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


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Currently Offered Variants 

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