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On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C1 C0 by default. Addresses for on-board I2C slave devices are listed in the table below:
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2019-09-17 | v79 | Martin Rohrmüller | - Updated according to PCN-20190110: eMMC, QSPI-Flash
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Jul 2019 | v.78 | Martin Rohrmüller | - Corrected PJTAG Mio Pin29 in table 8
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2019-05-08 | v.77 | John Hartfiel | - Corrected EEPROM I2C Address
- Correction USB PHY connection
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| v.74 | John Hartfiel | |
| v.73 | John Hartfiel | - typo correction
- update CPLD section
- add LEDs to component list
- add 3D picture of REV03 instead of REV01 picture
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| v.69 | Ali Naseri | |
| v.61 | John Hartfiel | - Rework chapter currently available products
- add PJTAG note to MIOtable
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2018-03-12 | v.54 |
| - Correction Power Rail Section
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2017-11-20 | v.51 | John Hartfiel | - Correction Default MIO Configuration Table
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2017-11-10 | v.50 | John Hartfiel | - Replace B2B connector section
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2017-10-18 | v.49 | John Hartfiel | |
2017-09-25 | v.48 | John Hartfiel | - Correction in the "Board to Board (B2B) I/Os" section
- Update in the "Variants Currently In Production" section
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2017-09-18 | v.47 | John Hartfiel | |
2017-08-30 | v.46 | Jan Kumann | |
| | John Hartfiel | - Correction in the "Key Features" section.
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2017-08-21 | v.34 | John Hartfiel | - "Initial delivery state" section updated.
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2017-08-21 | v.33 | Jan Kumann | - HW revision 02 block diagram added.
- Power distribution and power-on sequence diagram added.
- System Controller CPLD and DDR4 SDRAM sections added.
- TRM update to the template revision 1.6
- Weight section removed.
- Few minor corrections.
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| | John Hartfiel | - Style changes
- Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
- Correction of MIO SD Pin-out, System Controller chapter
- Update and new sub-sections on "On Board Peripherals and Interfaces" sections
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2017-08-07 | v.5 | Jan Kumann | |
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