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changes.mady.by.user John Hartfiel

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New Version 81

changes.mady.by.user Martin Rohrmüller

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USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 2552.000000 MHz oscillator (U15U14).

USB PHY connection

 PHY PinZYNQ PinB2B NameNotes
ULPIMIO52..63-Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK--52.000000 MHz from on-board oscillator (U14).
REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETBMIO25-Active low reset.
CLKOUTMIO52-Connected to 1.8V, selects reference clock operation mode.
DP, DM-OTG_D_P, OTG_D_NUSB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN-VBUS_V_ENExternal USB power switch active high enable signal, routed to JM3 pin 17.
VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID-OTG_IDFor an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

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Date

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Contributors

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  • typo and designator in section USB interface corrected
2019-10-30v.80John Hartfiel
  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version
--all

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